turnin a-3

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assets/a-2/exp1.gnuplot

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 set output "exp1.tex"
 set encoding utf8
-set terminal epslatex monochrome font "Arial,11" fontscale 1.0 size 12cm,8cm
+set terminal epslatex color font "Arial,11" fontscale 1.0 size 12cm,8cm
 set style data lines
-#set dashtype 1 ". "
+set style line 1 linetype 1 linewidth 1 linecolor rgb "magenta"
-#set dashtype 2 (2,4,2,6)
+set style line 2 linetype 1 linewidth 1 linecolor rgb "blue"
-#set dashtype 3 ".._"
+set style line 3 linetype 3 linewidth 1 linecolor rgb "green"
-set style line 1 
-set style line 2 dashtype 2
-set style line 3 dashtype 1
 set style line 91 linetype 1 linewidth 1 linecolor rgb "black"
 set style line 92 linetype 1 linewidth 0.5 linecolor rgb "gray20"
 set style line 93 linetype 1 linewidth 0.5 linecolor rgb "gray60"
@@ -31,9 +28,29 @@ x linetype 1 title "", \
 x / 2.2 linetype 2 title "", \
 x / 3.3 linetype 3 title "", \
 'exp1-theory.dat' using 1:($2 * 1000):($3 * 1000):($4 * 1000) linetype 1 linewidth 2 title "Theory (1.0k Ohm)" with yerrorbars, \
-'exp1-result.dat' using 1:($2 * 1000) title "Result (1.0k Ohm)" with points pt "x", \
+'exp1-result.dat' using 1:($2 * 1000) title "Result (1.0k Ohm)" with points, \
-'exp1-theory.dat' using 5:($6 * 1000):($7 * 1000):($8 * 1000) linetype 2 linewidth 4 title "Theory (2.2k Ohm)" with yerrorbars, \
+'exp1-theory.dat' using 5:($6 * 1000):($7 * 1000):($8 * 1000) linetype 2 linewidth 2 title "Theory (2.2k Ohm)" with yerrorbars, \
 'exp1-result.dat' using 3:($4 * 1000) title "Result (2.2k Ohm)" with points, \
-'exp1-theory.dat' using 9:($10 * 1000):($11 * 1000):($12 * 1000) linetype 3 linewidth 4 title "Theory (3.3k Ohm)" with yerrorbars, \
+'exp1-theory.dat' using 9:($10 * 1000):($11 * 1000):($12 * 1000) linetype 3 linewidth 2 title "Theory (3.3k Ohm)" with yerrorbars, \
 'exp1-result.dat' using 5:($6 * 1000) title "Result (3.3k Ohm)" with points
 
+
+#set multiplot layout 2,2 rowsfirst spacing 0.05
+#
+#set xlabel "Supply Voltage (V)"
+#set ylabel "Current (mA)" offset 1.0
+#
+#set label "1.0k Ohm" at graph 0.05,0.9 left boxed bs 2 front
+#plot 'exp1-theory.dat' using 1:($2 * 1000):($3 * 1000):($4 * 1000) linetype 1 title "Theory" with yerrorlines, \
+#'exp1-result.dat' using 1:($2 * 1000) title "Result" with points 
+#unset label
+#set label "2.2k Ohm" at graph 0.05,0.9 left boxed bs 2 front
+#plot 'exp1-theory.dat' using 5:($6 * 1000):($7 * 1000):($8 * 1000) linetype 1 title "Theory" with yerrorlines, \
+#'exp1-result.dat' using 3:($4 * 1000) title "Result" with points
+#set origin 0.2,0
+#unset label
+#set label "3.3k Ohm" at graph 0.05,0.9 left boxed bs 2 front
+#plot 'exp1-theory.dat' using 9:($10 * 1000):($11 * 1000):($12 * 1000) linetype 1 title "Theory" with yerrorlines, \
+#'exp1-result.dat' using 5:($6 * 1000) title "Result" with points
+#
+#unset multiplot

assets/a-2/exp1.tex

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+      \csname LTb\endcsname%%
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+      \csname LTb\endcsname%%
       \put(341,2508){\rotatebox{-270.00}{\makebox(0,0){\strut{}Current (mA)}}}%
       \put(3609,154){\makebox(0,0){\strut{}Supply Voltage (V)}}%
     }%

assets/a-3/exp2-1-bode.tex

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+      \expandafter\def\csname LT1\endcsname{\color{black}}%
+      \expandafter\def\csname LT2\endcsname{\color{black}}%
+      \expandafter\def\csname LT3\endcsname{\color{black}}%
+      \expandafter\def\csname LT4\endcsname{\color{black}}%
+      \expandafter\def\csname LT5\endcsname{\color{black}}%
+      \expandafter\def\csname LT6\endcsname{\color{black}}%
+      \expandafter\def\csname LT7\endcsname{\color{black}}%
+      \expandafter\def\csname LT8\endcsname{\color{black}}%
+    \fi
+  \fi
+    \setlength{\unitlength}{0.0500bp}%
+    \ifx\gptboxheight\undefined%
+      \newlength{\gptboxheight}%
+      \newlength{\gptboxwidth}%
+      \newsavebox{\gptboxtext}%
+    \fi%
+    \setlength{\fboxrule}{0.5pt}%
+    \setlength{\fboxsep}{1pt}%
+    \definecolor{tbcol}{rgb}{1,1,1}%
+\begin{picture}(6802.00,4534.00)%
+    \gplgaddtomacro\gplbacktext{%
+      \csname LTb\endcsname%%
+      \put(1078,2487){\makebox(0,0)[r]{\strut{}1e+02}}%
+      \put(1078,2944){\makebox(0,0)[r]{\strut{}1e+03}}%
+      \put(1078,3400){\makebox(0,0)[r]{\strut{}1e+04}}%
+      \put(1078,3857){\makebox(0,0)[r]{\strut{}1e+05}}%
+      \put(1078,4313){\makebox(0,0)[r]{\strut{}1e+06}}%
+      \put(1210,2267){\makebox(0,0){\strut{}}}%
+      \put(2066,2267){\makebox(0,0){\strut{}}}%
+      \put(2921,2267){\makebox(0,0){\strut{}}}%
+      \put(3777,2267){\makebox(0,0){\strut{}}}%
+      \put(4632,2267){\makebox(0,0){\strut{}}}%
+    }%
+    \gplgaddtomacro\gplfronttext{%
+      \csname LTb\endcsname%%
+      \put(5814,3510){\makebox(0,0)[r]{\strut{}1nF}}%
+      \put(5814,3290){\makebox(0,0)[r]{\strut{}100uF}}%
+      \put(209,3400){\rotatebox{-270.00}{\makebox(0,0){\strut{}Impedance ($\Omega$)}}}%
+    }%
+    \gplgaddtomacro\gplbacktext{%
+      \csname LTb\endcsname%%
+      \put(1078,704){\makebox(0,0)[r]{\strut{}  -30}}%
+      \put(1078,973){\makebox(0,0)[r]{\strut{}  0}}%
+      \put(1078,1241){\makebox(0,0)[r]{\strut{}  30}}%
+      \put(1078,1510){\makebox(0,0)[r]{\strut{}  60}}%
+      \put(1078,1778){\makebox(0,0)[r]{\strut{}  90}}%
+      \put(1078,2047){\makebox(0,0)[r]{\strut{}  120}}%
+      \put(2066,484){\makebox(0,0){\strut{}1k}}%
+      \put(2921,484){\makebox(0,0){\strut{}10k}}%
+      \put(3777,484){\makebox(0,0){\strut{}100k}}%
+      \put(4632,484){\makebox(0,0){\strut{}1M}}%
+      \put(1210,484){\makebox(0,0){\strut{}}}%
+    }%
+    \gplgaddtomacro\gplfronttext{%
+      \csname LTb\endcsname%%
+      \put(5814,1485){\makebox(0,0)[r]{\strut{}1nF}}%
+      \put(5814,1265){\makebox(0,0)[r]{\strut{}100uF}}%
+      \put(209,1375){\rotatebox{-270.00}{\makebox(0,0){\strut{}Phase ($\ \textdegree$)}}}%
+      \put(3050,154){\makebox(0,0){\strut{}Frequency (Hz)}}%
+    }%
+    \gplbacktext
+    \put(0,0){\includegraphics[width={340.10bp},height={226.70bp}]{./assets/a-3/exp2-1-bode}}%
+    \gplfronttext
+  \end{picture}%
+\endgroup

assets/a-3/exp2-1.gnuplot

@@ -0,0 +1,32 @@
+set output "exp2-1-bode.tex"
+
+load '../common.gnuplot'
+
+unset key
+set key center rmargin box height 1
+
+set log x
+set log y
+set xrange [1e2:2e6]
+
+set multiplot layout 2,1 rowsfirst
+
+set xlabel 
+set ylabel "Impedance ($\\Omega$)"
+set format x ""
+set format y "%.1g"
+
+plot "exp2-1_1nF-Z.txt" u 1:2 title "1nF" with points pt 2, "exp2-1_100uF-Z.txt" u 1:2 title "100uF" with points pt 4
+
+unset log y
+set xtics add ("1k" 1e3, "10k" 1e4, "100k" 1e5, "1M" 1e6)
+set yrange [-30:120]
+set ytics 30
+set xlabel "Frequency (Hz)"
+set ylabel "Phase ($\\ \\textdegree$)"
+set format y "  %.0f"
+
+plot "exp2-1_1nF.txt" u 1:4 title "1nF" with points pt 2, "exp2-1_100uF.txt" u 1:4 title "100uF" with points pt 4 
+
+unset multiplot
+

assets/a-3/exp2-1_100uF-Z.txt

@@ -0,0 +1,7 @@
+1000, 54484.076433
+5000, 54484.076433
+10000, 51530.120482
+50000, 50703.030303
+100000, 50133.333333
+500000, 49848.484848
+1000000, 49901.234568

assets/a-3/exp2-1_100uF.txt

@@ -0,0 +1,7 @@
+1000, 1.82, 1.57, 0
+5000, 1.82, 1.57, 0
+10000, 1.82, 1.66, 0
+50000, 1.78, 1.65, 0
+100000, 1.76, 1.65, 0
+500000, 1.75, 1.65, -1
+1000000, 1.72, 1.62, -4

assets/a-3/exp2-1_1nF-Z.txt

@@ -0,0 +1,7 @@
+1000, 156231.481481
+5000, 31626.168224
+10000, 15887.947269
+50000, 3139.245283
+100000, 1581.730769
+500000, 319.676113
+1000000, 167.779070

assets/a-3/exp2-1_1nF.txt

@@ -0,0 +1,7 @@
+1000, 3.59, 1.08/1000, 90
+5000, 3.60, 5.35/1000, 100
+10000, 3.59, 10.62/1000, 90
+50000, 3.54, 53/1000, 88
+100000, 3.50, 104/1000, 88
+500000, 3.36, 494/1000, 80
+1000000, 3.07, 860/1000, 70

assets/a-3/exp2-2-Z.txt

@@ -0,0 +1,7 @@
+1000, 563.356164
+5000, 2678.253968
+10000, 5084.545455
+50000, 12690.000000
+100000, 83928.571429
+500000, 31064.761905
+1000000, 14391.150442

assets/a-3/exp2-2-bode.tex

@@ -0,0 +1,126 @@
+% GNUPLOT: LaTeX picture with Postscript
+\begingroup
+  \fontfamily{Arial}%
+  \selectfont
+  \makeatletter
+  \providecommand\color[2][]{%
+    \GenericError{(gnuplot) \space\space\space\@spaces}{%
+      Package color not loaded in conjunction with
+      terminal option `colourtext'%
+    }{See the gnuplot documentation for explanation.%
+    }{Either use 'blacktext' in gnuplot or load the package
+      color.sty in LaTeX.}%
+    \renewcommand\color[2][]{}%
+  }%
+  \providecommand\includegraphics[2][]{%
+    \GenericError{(gnuplot) \space\space\space\@spaces}{%
+      Package graphicx or graphics not loaded%
+    }{See the gnuplot documentation for explanation.%
+    }{The gnuplot epslatex terminal needs graphicx.sty or graphics.sty.}%
+    \renewcommand\includegraphics[2][]{}%
+  }%
+  \providecommand\rotatebox[2]{#2}%
+  \@ifundefined{ifGPcolor}{%
+    \newif\ifGPcolor
+    \GPcolorfalse
+  }{}%
+  \@ifundefined{ifGPblacktext}{%
+    \newif\ifGPblacktext
+    \GPblacktexttrue
+  }{}%
+  % define a \g@addto@macro without @ in the name:
+  \let\gplgaddtomacro\g@addto@macro
+  % define empty templates for all commands taking text:
+  \gdef\gplbacktext{}%
+  \gdef\gplfronttext{}%
+  \makeatother
+  \ifGPblacktext
+    % no textcolor at all
+    \def\colorrgb#1{}%
+    \def\colorgray#1{}%
+  \else
+    % gray or color?
+    \ifGPcolor
+      \def\colorrgb#1{\color[rgb]{#1}}%
+      \def\colorgray#1{\color[gray]{#1}}%
+      \expandafter\def\csname LTw\endcsname{\color{white}}%
+      \expandafter\def\csname LTb\endcsname{\color{black}}%
+      \expandafter\def\csname LTa\endcsname{\color{black}}%
+      \expandafter\def\csname LT0\endcsname{\color[rgb]{1,0,0}}%
+      \expandafter\def\csname LT1\endcsname{\color[rgb]{0,1,0}}%
+      \expandafter\def\csname LT2\endcsname{\color[rgb]{0,0,1}}%
+      \expandafter\def\csname LT3\endcsname{\color[rgb]{1,0,1}}%
+      \expandafter\def\csname LT4\endcsname{\color[rgb]{0,1,1}}%
+      \expandafter\def\csname LT5\endcsname{\color[rgb]{1,1,0}}%
+      \expandafter\def\csname LT6\endcsname{\color[rgb]{0,0,0}}%
+      \expandafter\def\csname LT7\endcsname{\color[rgb]{1,0.3,0}}%
+      \expandafter\def\csname LT8\endcsname{\color[rgb]{0.5,0.5,0.5}}%
+    \else
+      % gray
+      \def\colorrgb#1{\color{black}}%
+      \def\colorgray#1{\color[gray]{#1}}%
+      \expandafter\def\csname LTw\endcsname{\color{white}}%
+      \expandafter\def\csname LTb\endcsname{\color{black}}%
+      \expandafter\def\csname LTa\endcsname{\color{black}}%
+      \expandafter\def\csname LT0\endcsname{\color{black}}%
+      \expandafter\def\csname LT1\endcsname{\color{black}}%
+      \expandafter\def\csname LT2\endcsname{\color{black}}%
+      \expandafter\def\csname LT3\endcsname{\color{black}}%
+      \expandafter\def\csname LT4\endcsname{\color{black}}%
+      \expandafter\def\csname LT5\endcsname{\color{black}}%
+      \expandafter\def\csname LT6\endcsname{\color{black}}%
+      \expandafter\def\csname LT7\endcsname{\color{black}}%
+      \expandafter\def\csname LT8\endcsname{\color{black}}%
+    \fi
+  \fi
+    \setlength{\unitlength}{0.0500bp}%
+    \ifx\gptboxheight\undefined%
+      \newlength{\gptboxheight}%
+      \newlength{\gptboxwidth}%
+      \newsavebox{\gptboxtext}%
+    \fi%
+    \setlength{\fboxrule}{0.5pt}%
+    \setlength{\fboxsep}{1pt}%
+    \definecolor{tbcol}{rgb}{1,1,1}%
+\begin{picture}(6802.00,4534.00)%
+    \gplgaddtomacro\gplbacktext{%
+      \csname LTb\endcsname%%
+      \put(1078,2487){\makebox(0,0)[r]{\strut{}1e+02}}%
+      \put(1078,3096){\makebox(0,0)[r]{\strut{}1e+03}}%
+      \put(1078,3704){\makebox(0,0)[r]{\strut{}1e+04}}%
+      \put(1078,4313){\makebox(0,0)[r]{\strut{}1e+05}}%
+      \put(1210,2267){\makebox(0,0){\strut{}}}%
+      \put(2418,2267){\makebox(0,0){\strut{}}}%
+      \put(3626,2267){\makebox(0,0){\strut{}}}%
+      \put(4834,2267){\makebox(0,0){\strut{}}}%
+      \put(6041,2267){\makebox(0,0){\strut{}}}%
+    }%
+    \gplgaddtomacro\gplfronttext{%
+      \csname LTb\endcsname%%
+      \put(2266,4030){\makebox(0,0)[r]{\strut{}100mH}}%
+      \put(209,3400){\rotatebox{-270.00}{\makebox(0,0){\strut{}Impedance ($\Omega$)}}}%
+    }%
+    \gplgaddtomacro\gplbacktext{%
+      \csname LTb\endcsname%%
+      \put(1078,838){\makebox(0,0)[r]{\strut{}  -80}}%
+      \put(1078,1107){\makebox(0,0)[r]{\strut{}  -40}}%
+      \put(1078,1376){\makebox(0,0)[r]{\strut{}  0}}%
+      \put(1078,1644){\makebox(0,0)[r]{\strut{}  40}}%
+      \put(1078,1913){\makebox(0,0)[r]{\strut{}  80}}%
+      \put(2418,484){\makebox(0,0){\strut{}1k}}%
+      \put(3626,484){\makebox(0,0){\strut{}10k}}%
+      \put(4834,484){\makebox(0,0){\strut{}100k}}%
+      \put(6041,484){\makebox(0,0){\strut{}1M}}%
+      \put(1210,484){\makebox(0,0){\strut{}}}%
+    }%
+    \gplgaddtomacro\gplfronttext{%
+      \csname LTb\endcsname%%
+      \put(2266,1764){\makebox(0,0)[r]{\strut{}100mH}}%
+      \put(209,1375){\rotatebox{-270.00}{\makebox(0,0){\strut{}Phase ($\ \textdegree$)}}}%
+      \put(3807,154){\makebox(0,0){\strut{}Frequency (Hz)}}%
+    }%
+    \gplbacktext
+    \put(0,0){\includegraphics[width={340.10bp},height={226.70bp}]{./assets/a-3/exp2-2-bode}}%
+    \gplfronttext
+  \end{picture}%
+\endgroup

assets/a-3/exp2-2.gnuplot

@@ -0,0 +1,31 @@
+set output "exp2-2-bode.tex"
+
+load '../common.gnuplot'
+
+unset key
+set key top left box height 1 width 2
+
+set log x
+set log y
+set xrange [1e2:2e6]
+
+set multiplot layout 2,1 rowsfirst
+
+set xlabel 
+set ylabel "Impedance ($\\Omega$)"
+set format x ""
+set format y "%.1g"
+
+plot "exp2-2-Z.txt" u 1:2 title "100mH" with points pt 5
+
+unset log y
+set xtics add ("1k" 1e3, "10k" 1e4, "100k" 1e5, "1M" 1e6)
+set yrange [-100:100]
+set ytics 40
+set xlabel "Frequency (Hz)"
+set ylabel "Phase ($\\ \\textdegree$)"
+set format y "  %.0f"
+
+plot "exp2-2.txt" u 1:4 title "100mH" with points pt 5
+
+unset multiplot

assets/a-3/exp2-2.txt

@@ -0,0 +1,7 @@
+1000, 3.50, 0.292, -75
+5000, 3.59, 0.063, -87
+10000, 3.57, 0.033, -88
+50000, 3.51, 0.013, -88
+100000, 3.50, 0.00196, -90
+500000, 3.47, 0.00525, 90
+1000000, 3.46, 0.0113, 85

assets/a-3/generate-plot.sh

@@ -0,0 +1,4 @@
+gnuplot exp2-1.gnuplot
+gnuplot exp2-2.gnuplot
+sed -i -f patch-exp2-1.sed exp2-1-bode.tex
+sed -i -f patch-exp2-2.sed exp2-2-bode.tex

assets/a-3/patch-exp2-1.sed

@@ -0,0 +1 @@
+s/exp2-1-bode/.\/assets\/a-3\/exp2-1-bode/g;

assets/a-3/patch-exp2-2.sed

@@ -0,0 +1 @@
+s/exp2-2-bode/.\/assets\/a-3\/exp2-2-bode/g;

assets/t-1/exp1.eps

@@ -1,7 +1,7 @@
 %!PS-Adobe-2.0 EPSF-2.0
 %%Title: exp1.tex
 %%Creator: gnuplot 6.0 patchlevel 4
-%%CreationDate: Sat Jun 13 21:52:51 2026
+%%CreationDate: Tue May 26 00:17:35 2026
 %%DocumentFonts: 
 %%BoundingBox: 50 50 390 276
 %%EndComments
@@ -441,7 +441,7 @@ SDict begin [
   /Creator (gnuplot 6.0 patchlevel 4)
 %  /Producer (gnuplot)
 %  /Keywords ()
-  /CreationDate (Sat Jun 13 21:52:51 2026)
+  /CreationDate (Tue May 26 00:17:35 2026)
   /DOCINFO pdfmark
 end
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+-63 0 V
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+5459 0 V
+stroke
+1.000 UL
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+stroke
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-1.000 UP
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-1401 1913 M
+1632 1913 M
-356 598 V
+340 598 V
-359 346 V
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-355 63 V
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assets/t-1/exp1.gnuplot

@@ -1,8 +1,7 @@
 load '../common.gnuplot'
 
 set output "exp1.tex"
-set xtics 0, 2, 8
+set xtics 0, 3, 8
-set ytics 0, 1, 3
 set xrange [0:8]
 set yrange [0:3]
 
@@ -11,7 +10,4 @@ set key top left Left reverse
 set xlabel "Supply Voltage (V)"
 set ylabel "LED Voltage (V)" 
 
-set pointsize 1
+plot 'forward.dat' using 3:2 linetype 1 linewidth 2 title "" with lines
-set style line 4 linetype 1 pointtype 6 linewidth 2
-
-plot 'forward.dat' using 3:2 title "" with linespoints ls 4

assets/t-1/exp1.tex

@@ -85,20 +85,21 @@
 \begin{picture}(6802.00,4534.00)%
     \gplgaddtomacro\gplbacktext{%
       \csname LTb\endcsname%%
-      \put(550,704){\makebox(0,0)[r]{\strut{}$0$}}%
+      \put(814,704){\makebox(0,0)[r]{\strut{}$0$}}%
-      \put(550,1907){\makebox(0,0)[r]{\strut{}$1$}}%
+      \put(814,1306){\makebox(0,0)[r]{\strut{}$0.5$}}%
-      \put(550,3110){\makebox(0,0)[r]{\strut{}$2$}}%
+      \put(814,1907){\makebox(0,0)[r]{\strut{}$1$}}%
-      \put(550,4313){\makebox(0,0)[r]{\strut{}$3$}}%
+      \put(814,2509){\makebox(0,0)[r]{\strut{}$1.5$}}%
-      \put(682,484){\makebox(0,0){\strut{}$0$}}%
+      \put(814,3110){\makebox(0,0)[r]{\strut{}$2$}}%
-      \put(2113,484){\makebox(0,0){\strut{}$2$}}%
+      \put(814,3712){\makebox(0,0)[r]{\strut{}$2.5$}}%
-      \put(3544,484){\makebox(0,0){\strut{}$4$}}%
+      \put(814,4313){\makebox(0,0)[r]{\strut{}$3$}}%
-      \put(4974,484){\makebox(0,0){\strut{}$6$}}%
+      \put(946,484){\makebox(0,0){\strut{}$0$}}%
-      \put(6405,484){\makebox(0,0){\strut{}$8$}}%
+      \put(2993,484){\makebox(0,0){\strut{}$3$}}%
+      \put(5040,484){\makebox(0,0){\strut{}$6$}}%
     }%
     \gplgaddtomacro\gplfronttext{%
       \csname LTb\endcsname%%
       \put(209,2508){\rotatebox{-270.00}{\makebox(0,0){\strut{}LED Voltage (V)}}}%
-      \put(3543,154){\makebox(0,0){\strut{}Supply Voltage (V)}}%
+      \put(3675,154){\makebox(0,0){\strut{}Supply Voltage (V)}}%
     }%
     \gplbacktext
     \put(0,0){\includegraphics[width={340.10bp},height={226.70bp}]{./assets/t-1/exp1}}%

assets/t-1/exp2.eps

@@ -1,7 +1,7 @@
 %!PS-Adobe-2.0 EPSF-2.0
 %%Title: exp2.tex
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-%%CreationDate: Sat Jun 13 21:54:46 2026
+%%CreationDate: Tue May 26 14:24:41 2026
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@@ -441,7 +441,7 @@ SDict begin [
   /Creator (gnuplot 6.0 patchlevel 4)
 %  /Producer (gnuplot)
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-  /CreationDate (Sat Jun 13 21:54:46 2026)
+  /CreationDate (Tue May 26 14:24:41 2026)
   /DOCINFO pdfmark
 end
 } ifelse
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-2194 1585 Circle
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assets/t-1/exp2.gnuplot

@@ -2,7 +2,6 @@ load '../common.gnuplot'
 
 set output "exp2.tex"
 set xtics -3,1,0
-set ytics -3,1,0
 set xrange [-4:0]
 set yrange [-4:0]
 
@@ -10,6 +9,5 @@ set key top left Left reverse
 
 set xlabel "Supply Voltage (V)"
 set ylabel "LED Voltage (V)"
-set style line 1 pointtype 6 linewidth 2
 
-plot 'reverse.dat' using 1:($3 - $2) title "" with linespoints ls 1
+plot 'reverse.dat' using 1:($3 - $2) linetype 1 linewidth 2 title "" with lines

assets/t-1/exp2.tex

@@ -85,19 +85,24 @@
 \begin{picture}(6802.00,4534.00)%
     \gplgaddtomacro\gplbacktext{%
       \csname LTb\endcsname%%
-      \put(682,1606){\makebox(0,0)[r]{\strut{}$-3$}}%
+      \put(946,704){\makebox(0,0)[r]{\strut{}$-4$}}%
-      \put(682,2509){\makebox(0,0)[r]{\strut{}$-2$}}%
+      \put(946,1155){\makebox(0,0)[r]{\strut{}$-3.5$}}%
-      \put(682,3411){\makebox(0,0)[r]{\strut{}$-1$}}%
+      \put(946,1606){\makebox(0,0)[r]{\strut{}$-3$}}%
-      \put(682,4313){\makebox(0,0)[r]{\strut{}$0$}}%
+      \put(946,2057){\makebox(0,0)[r]{\strut{}$-2.5$}}%
-      \put(2212,484){\makebox(0,0){\strut{}$-3$}}%
+      \put(946,2509){\makebox(0,0)[r]{\strut{}$-2$}}%
-      \put(3610,484){\makebox(0,0){\strut{}$-2$}}%
+      \put(946,2960){\makebox(0,0)[r]{\strut{}$-1.5$}}%
-      \put(5007,484){\makebox(0,0){\strut{}$-1$}}%
+      \put(946,3411){\makebox(0,0)[r]{\strut{}$-1$}}%
+      \put(946,3862){\makebox(0,0)[r]{\strut{}$-0.5$}}%
+      \put(946,4313){\makebox(0,0)[r]{\strut{}$0$}}%
+      \put(2410,484){\makebox(0,0){\strut{}$-3$}}%
+      \put(3742,484){\makebox(0,0){\strut{}$-2$}}%
+      \put(5073,484){\makebox(0,0){\strut{}$-1$}}%
       \put(6405,484){\makebox(0,0){\strut{}$0$}}%
     }%
     \gplgaddtomacro\gplfronttext{%
       \csname LTb\endcsname%%
       \put(209,2508){\rotatebox{-270.00}{\makebox(0,0){\strut{}LED Voltage (V)}}}%
-      \put(3609,154){\makebox(0,0){\strut{}Supply Voltage (V)}}%
+      \put(3741,154){\makebox(0,0){\strut{}Supply Voltage (V)}}%
     }%
     \gplbacktext
     \put(0,0){\includegraphics[width={340.10bp},height={226.70bp}]{./assets/t-1/exp2}}%

assets/t-2/7seg_a-f.txt

@@ -0,0 +1,8 @@
+(A, B, C, D): (a, b, c, d, e, f, g)
+(0, 1, 0, 1): (1, 1, 1, 0, 1, 1, 1) // 0x0A
+(1, 1, 0, 1): (0, 0, 1, 1, 1, 1, 1) // 0x0b
+(0, 0, 1, 1): (1, 0, 0, 1, 1, 1, 0) // 0x0C
+(1, 0, 1, 1): (0, 1, 1, 1, 1, 0, 1) // 0x0d
+(0, 1, 1, 1): (1, 0, 0, 1, 1, 1, 1) // 0x0E
+(1, 1, 1, 1): (1, 0, 0, 0, 1, 1, 1) // 0x0F
+

bibs/a-3.bib

@@ -0,0 +1,22 @@
+@book{brit-time_constant,
+    title={ブリタニカ国際大百科事典 小項目電子辞書版},
+    author={Ltd., Britannica Japan Co. and Inc., Encyclop\ae{}dia Britannica},
+    publisher={Britannica Japan Co., Ltd.},
+    year={2016}
+}
+@inbook{ac-theory:impedance,
+    title={基礎からの交流理論},
+    author={小郷 寛 and 小亀 英己 and 石亀 篤司},
+    publisher={電気学会 and オーム社},
+    year={2023},
+    month={04},
+    chapter={3}
+}
+@inbook{ac-theory:rlc-parallel,
+    title={基礎からの交流理論},
+    author={小郷 寛 and 小亀 英己 and 石亀 篤司},
+    publisher={電気学会 and オーム社},
+    year={2023},
+    month={04},
+    pages={77-80}
+}

bibs/t-2.bib

@@ -0,0 +1,71 @@
+@inbook{digital-circuit:digital,
+    title={ゼロから学ぶディジタル論理回路},
+    author={秋田 純一},
+    publisher={株式会社講談社},
+    year={2005},
+    month={06},
+    pages={7-11}
+}
+@inbook{digital-circuit:basic-logic,
+    title={ゼロから学ぶディジタル論理回路},
+    author={秋田 純一},
+    publisher={株式会社講談社},
+    year={2005},
+    month={06},
+    pages={17-23}
+}
+@inbook{digital-circuit:gate-ic,
+    title={ゼロから学ぶディジタル論理回路},
+    author={秋田 純一},
+    publisher={株式会社講談社},
+    year={2005},
+    month={06},
+    pages={31-34}
+}
+@inbook{digital-circuit:xor,
+    title={ゼロから学ぶディジタル論理回路},
+    author={秋田 純一},
+    publisher={株式会社講談社},
+    year={2005},
+    month={06},
+    pages={47-49}
+}
+@inbook{digital-circuit:truth-table,
+    title={ゼロから学ぶディジタル論理回路},
+    author={秋田 純一},
+    publisher={株式会社講談社},
+    year={2005},
+    month={06},
+    pages={49-54}
+}
+@inbook{digital-circuit:karnaugh-map,
+    title={ゼロから学ぶディジタル論理回路},
+    author={秋田 純一},
+    publisher={株式会社講談社},
+    year={2005},
+    month={06},
+    pages={55-61}
+}
+@inbook{digital-circuit:state-transition,
+    title={ゼロから学ぶディジタル論理回路},
+    author={秋田 純一},
+    publisher={株式会社講談社},
+    year={2005},
+    month={06},
+    pages={101-106}
+}
+@inbook{digital-circuit:sequential-logic,
+    title={ゼロから学ぶディジタル論理回路},
+    author={秋田 純一},
+    publisher={株式会社講談社},
+    year={2005},
+    month={06},
+    pages={77-78}
+}
+@online{tc74hc74,
+    title={TC74HC74AP/AF},
+    author={TOSHIBA Semiconductor},
+    year={2014},
+    month={03},
+    url={https://akizukidenshi.com/goodsaffix/TC74HC74AP_datasheet_ja_20140301.pdf}
+}

report_a-3.tex

@@ -0,0 +1,91 @@
+\documentclass[japanese,xelatex,a4paper,10.5pt,ja=standard]{bxjsarticle}
+
+\usepackage{tex/preamble}
+\usepackage{tex/experiment-title}
+\usepackage{amsmath}
+\usepackage{amssymb}
+\usepackage{cleveref}
+\usepackage{multirow}
+\usepackage{pgf}
+\usepackage{pgffor}
+\usepackage{circuitikz}
+\usepackage{subcaption}
+\usepackage{tex/depD-bib}
+
+\renewcommand\figurename{Fig. }
+\renewcommand\tablename{Table }
+\renewcommand\theequation{\thesection-\arabic{equation}}
+\renewcommand\thefigure{\thesection-\arabic{figure}}
+\renewcommand\thetable{\thesection-\arabic{table}}
+
+\crefdefaultlabelformat{#1}
+\crefname{figure}{Fig.}{Fig.}
+\Crefname{figure}{Fig.}{Fig.}
+\crefname{table}{Table}{Tables}
+\Crefname{table}{Table}{Tables}
+\crefname{equation}{Eq.}{Eq.}
+\Crefname{equation}{Eq.}{Eq.}
+\creflabelformat{equation}{(#1)}
+
+\newcommand\resetrefcounter{
+    \setcounter{equation}{0}
+    \setcounter{figure}{0}
+    \setcounter{table}{0}
+}
+
+\reportauthor{柴田健琉}
+\reporttitle{抵抗・コンデンサ・インダクタの特性}
+\reportdate{2026年}{07月}{17日}
+\turnindate{2026年}{08月}{10日}
+\schoolyear{2026}
+\grade{3}
+\department{電子制御工学科}
+\subject{電子制御工学実験１}
+\reportid{A-3}
+\expgroup{4班}
+\seatingnum{15}
+\addResearcher{後藤 昊大}
+\addResearcher{佐藤 暖斗}
+\addResearcher{高橋 健太}
+\addExperimentDate{2026年 06月 30日}
+\addExperimentDate{2026年 07月 07日}
+\addExperimentDate{2026年 07月 08日}
+\addExperimentDate{2026年 07月 14日}
+
+\addbibresource{./bibs/a-3.bib}
+
+\begin{document}
+    \experimentTitle
+
+    \section{実験目的}
+
+    今回の実験では，電気回路の基本的な受動素子の特性や動作を確認するために行った．
+
+    \input{sections/a-3/theory}
+    \resetrefcounter
+
+    \input{sections/a-3/exp-detail}
+    \resetrefcounter
+
+    \newpage
+
+    \input{sections/a-3/exp-result}
+    \resetrefcounter
+
+    \input{sections/a-3/reflection}
+    \resetrefcounter
+    \newpage
+
+    \section{まとめ}
+
+    今回の実験より以下の事が分かった：
+
+    \begin{itemize}
+        \item {回路素子の特性は周波数ごとに様々な様子を見せる}
+        \item {インダクタやコンデンサの定数は有効な周波数での特性図から読み取れる}
+        \item {フィルタの設計にはQ値や半値幅などの設定が重要となる}
+    \end{itemize}
+
+    \printbibliography[title={参考文献}]{}
+
+\end{document}

report_t-2.tex

@@ -0,0 +1,64 @@
+\documentclass[japanese,xelatex,a4paper,10.5pt,ja=standard]{bxjsarticle}
+
+\usepackage{tex/preamble}
+\usepackage{tex/experiment-title}
+\usepackage{amsmath}
+\usepackage{amssymb}
+\usepackage{array}
+\usepackage{multirow}
+\usepackage{subcaption}
+\usepackage{pgfmath}
+\usepackage{pgffor}
+\usepackage{tex/depD-bib}
+\usepackage{tex/depD-format}
+
+\usetikzlibrary{automata}
+
+\reportauthor{柴田健琉}
+\reporttitle{ディジタル回路}
+\reportdate{2026年}{06月}{20日}
+\turnindate{2026年}{06月}{30日}
+\schoolyear{2026}
+\grade{3}
+\department{電子制御工学科}
+\subject{電子制御工学実験1}
+\reportid{T-2}
+\expgroup{-}
+\seatingnum{15}
+\addExperimentDate{2026年 06月 02日}
+\addExperimentDate{2026年 06月 16日}
+\addExperimentDate{2026年 06月 23日}
+
+\addbibresource{./bibs/t-2.bib}
+
+\begin{document}
+    \experimentTitle
+
+    \section{実験目的}
+
+    今回の実験ではディジタル回路の基礎と応用について学ぶために行った.
+
+    \input{./sections/t-2/theory}
+    \resetrefcounter
+
+    \input{./sections/t-2/exp-detail}
+    \resetrefcounter
+
+    \input{./sections/t-2/exp-result}
+    \resetrefcounter
+
+    \input{./sections/t-2/reflection}
+    \resetrefcounter
+
+    \section{まとめ}
+
+    今回の実験で以下の事実を確認した:
+    
+    \begin{itemize}
+        \item{各種論理ゲートは組み合わせることで多種多様な動作をする回路を構築可能である}
+        \item{ブール代数の諸法則・諸定理で論理回路の規模・複雑性を調整することができる}
+        \item{順序回路の動作の記述には状態遷移図・表が有効である}
+    \end{itemize}
+
+    \printbibliography[title={参考文献}]{}
+\end{document}

sections/a-2/exp-result.tex

@@ -7,7 +7,7 @@
 \begin{figure}[tbh]
     \centering
     \input{assets/a-2/exp1}
-    \caption{Voltage v.s. Current of Differenct Resistors with Theoretical Values and $\pm 5\%$ Error Ranges}
+    \caption{Voltage v.s. Current of Differenct Resistors with Theoretical Values and Error Ranges}
     \label{fig:v-i-r}
 \end{figure}
 
@@ -25,9 +25,9 @@ $E_1 = 15.000 \ \text{V}, \ E_2 = 3.005 \ \text{V}$の時，各抵抗での電
 
 \begin{table}[ht]
     \centering
-    \caption{Voltage and Current on each Resistors in Circuit (a)}
+    \caption{Result of Experiment \# 2 with Circuit (a)}
     \label{tab:exp2-res1}
-    \begin{tabular}{crr}
+    \begin{tabular}{c|c|c}
         \hline
         Resistor & Voltage $[\text{V}]$ & Current $[\text{mA}]$ \\
         \hline
@@ -48,9 +48,9 @@ $E_1 = 15.000 \ \text{V}, \ E_2 = -3.007 \ \text{V}$の時，各抵抗での電
 
 \begin{table}[ht]
     \centering
-    \caption{Voltage and Current on each Resistors in Circuit (b)}
+    \caption{Result of Experiment \# 2 with Circuit (b)}
     \label{tab:exp2-res2}
-    \begin{tabular}{crr}
+    \begin{tabular}{c|c|c}
         \hline
         Resistor & Voltage $[\text{V}]$ & Current $[\text{mA}]$ \\
         \hline
@@ -76,9 +76,9 @@ $E_1 = 15.000 \ \text{V}$での各抵抗にかかった電流・電圧は\cref{t
 
 \begin{table}[ht]
     \centering
-    \caption{Voltage and Current of each Resistors in Circuit (a) with $E_1$ as Voltage Source}
+    \caption{Result of Experiment \# 3 with $E_1$ as Voltage Source}
     \label{tab:exp3-res1}
-    \begin{tabular}{crr}
+    \begin{tabular}{c|c|c}
         \hline
         Resistor & Voltage $[\text{V}]$ & Current $[\text{mA}]$ \\
         \hline
@@ -95,9 +95,9 @@ $E_2 = 3.004 \ \text{V}$での各抵抗にかかった電流・電圧は\cref{ta
 
 \begin{table}[ht]
     \centering
-    \caption{Voltage and Current of each Resistors in Circuit (a) with $E_2$ as Voltage Source}
+    \caption{Result of Experiment \# 3 with $E_2$ as Voltage Source}
     \label{tab:exp3-res2}
-    \begin{tabular}{crr}
+    \begin{tabular}{c|c|c}
         \hline
         Resistor & Voltage $[\text{V}]$ & Current $[\text{mA}]$ \\
         \hline
@@ -118,7 +118,7 @@ $E_2 = 3.004 \ \text{V}$での各抵抗にかかった電流・電圧は\cref{ta
     \centering
     \caption{Voltage and Current of Load}
     \label{tab:exp4-res}
-    \begin{tabular}{crr}
+    \begin{tabular}{c|c|c}
         \hline
         Circuit & Voltage $[\text{V}]$ & Current $[\text{mA}]$ \\
         \hline

sections/a-2/reflection.tex

@@ -15,7 +15,7 @@
 
 \begin{table}[!ht]
     \centering
-    \caption{Current and Power of Resistors with Tenth of Resistance}
+    \caption{Current and Power of Resistors with tenth of resistance}
     \label{tab:v-i-r-tenth}
     \begin{tabular}{c|r|r|r|r|r|r}
         \hline
@@ -42,9 +42,9 @@
 
 \begin{table}[!ht]
     \centering
-    \caption{Applying Kirchhoff's Current Law at Point (b) to each Circuits}
+    \caption{Applying Kirchhoff's Current Law at Point (b) in each Circuit}
     \label{tab:current-in-b}
-    \begin{tabular}{cr}
+    \begin{tabular}{c|c}
         \hline
         Circuit & Current $[\text{mA}]$ \\
         \hline
@@ -58,13 +58,13 @@
 
 \begin{table}[!ht]
     \centering
-    \caption{Applying Kirchhoff's Voltage Law to each Loops}
+    \caption{Applying Kirchhoff's Voltage Law on each Loop}
     \label{tab:voltage-in-loops}
-    \begin{tabular}{crr}
+    \begin{tabular}{c|c|c}
         \hline
         Loop & Circuit (a) $[\text{V}]$ & Circuit (b) $[\text{V}]$ \\
         \hline
-        abef & 0.010 & 0.010 \\
+        abef & 0.01 & 0.01 \\
         bcde & -0.005 & 0.007 \\
         acdf & 0.005 & -0.017 \\
         \hline
@@ -92,13 +92,13 @@
 
 \begin{table}[!ht]
     \centering
-    \caption{Percentage Differences of Experiment \# 3 from Experiment \# 2 on Circuit (a)}
+    \caption{Percentage Difference of Experiment \# 3 from Experiment \# 2 on Circuit (a)}
     \label{tab:exp3-exp2-diff}
-    \begin{tabular}{cr}
+    \begin{tabular}{c|c}
         \hline
         Measurement & Difference $(\%)$ \\
         \hline
-        $V_{R_1}$ & 0.00 \\
+        $V_{R_1}$ & 0 \\
         $V_{R_2}$ & +1.54 \\
         $V_{R_3}$ & -0.23 \\
         $I_{R_1}$ & +0.30 \\
@@ -121,7 +121,7 @@
     \begin{minipage}[h]{0.9\linewidth}
         \centering
         \begin{circuitikz}
-            \draw (0,0) to [battery1, l={$E$},invert] ++(0,2) to [R={$R_i$}] ++(0,2);
+            \draw (0,0) to [battery1={$E$},invert] ++(0,2) to [R={$R_i$}] ++(0,2);
             \draw (0,0) to [short, -o] ++(2,0);
             \draw (0,4) to [short, -o] ++(2,0);
 
@@ -137,7 +137,7 @@
     \begin{minipage}[h]{0.9\linewidth}
         \centering
         \begin{circuitikz}
-            \draw (0,0) to [isourceAM, l={$I$}] ++(0,2);
+            \draw (0,0) to [isourceAM={$I$}] ++(0,2);
             \draw (2,0) to [R={$R_i$}] ++(0,2);
             \draw (0,0) to [short, -*] ++(2,0) to [short, -o] ++(2,0);
             \draw (0,2) to [short, -*] ++(2,0) to [short, -o] ++(2,0);
@@ -161,9 +161,9 @@
 
 \begin{table}[!ht]
     \centering
-    \caption{Percentage Differences of Original and Equivalent Circuit of Experiment \# 4}
+    \caption{Percentage Difference of Original and Equivalent Circuit of Experiment \# 4}
     \label{tab:exp4-diff}
-    \begin{tabular}{cr}
+    \begin{tabular}{c|c}
         \hline
         Measurement & Difference $[\%]$ \\
         \hline

sections/a-3/exp-detail.tex

@@ -0,0 +1,86 @@
+\section{実験条件・実験手順}
+
+\subsection{実験器具}
+
+\begin{itemize}
+    \item{$10 \ \text{k}\Omega$ 抵抗器}
+    \item{$47 \ \Omega$ 抵抗器}
+    \item{$1 \ \text{nF}$ コンデンサ}
+    \item{$100 \ \mu\text{F}$ コンデンサ}
+    \item{$100 \ \text{mH}$ インダクタ}
+    \item{ブレッドボード}
+    \item{ジャンパーワイヤ}
+    \item{ADALM2000}
+    \item{オシロスコープ}
+    \item{ファンクションジェネレータ}
+\end{itemize}
+
+\subsection{実験1-1}
+
+ADALM2000を使用してRC直列回路に矩形波を入力し, 応答波形を観察する.
+なお, 矩形波の周期は$2t$とし, $t$には回路の時定数の1倍, 5倍, 15倍の値を使用する.
+
+抵抗器には10 $\text{k}\Omega$を, コンデンサには1 nFのものを使用した.
+
+\subsection{実験1-2}
+
+ADALM2000を使用してRL直列回路に矩形波を入力し, 応答波形を観察する.
+なお, 矩形波の周期は$2t$とし, $t$には回路の時定数の0.5倍, 5倍, 25倍の値を使用する.
+
+抵抗器には10 $\text{k}\Omega$を, インダクタには100 mHのものを使用した.
+
+\subsection{実験2-1}
+
+\Cref{fig:exp21-cd}のRC直列回路を作成し, ファンクションジェネレータを使用して正弦波を回路に入力し, オシロスコープとマルチメータで1 kHzから1 MHzまでの回路のインピーダンス特性を測定する.
+オシロスコープで入力信号と抵抗器の電圧との位相差を測定し, マルチメータで抵抗器の電圧を測定する. 電流は抵抗器の抵抗値と電圧から求める.
+なお, 入力周波数が10 kHzを超えるとマルチメータの読みが不正確になるのでオシロスコープで10 kHz以上の信号を測定した.
+コンデンサの静電容量は1 nFのものと$100 \ \mu\text{F}$のものをそれぞれ測定する.
+
+\begin{figure}[H]
+    \centering
+    \begin{circuitikz}
+        \ctikzset{bipoles/oscope/waveform=sin}
+        \draw (0,0) node[ground]{} to [vsourcesin, l={Fn}] ++(0,4) -- ++(2,0) to [C, l={$C$}] ++(0,-2) coordinate (vr) to [R, l={$47 \ \Omega$}] ++(0,-2) node[ground]{};
+        \draw (vr) to [short, *-] ++(2,0) to [short,-*] ++(0,0.5) node[oscopeshape,anchor=in 1](os){$V_R$} (os.in 2) to [short, *-] ++(0,-0.5) node[ground]{};
+    \end{circuitikz}
+    \caption{Circuit Diagram for Experiment 2-1}
+    \label{fig:exp21-cd}
+\end{figure}
+
+\subsection{実験2-2}
+
+\Cref{fig:exp22-cd}のRL直列回路を作成し, 実験2-1同様の手順でインダクタのインピーダンス特性を測定する.
+インダクタは100 mHのものを使用した.
+
+\begin{figure}[H]
+    \centering
+    \begin{circuitikz}
+        \ctikzset{bipoles/oscope/waveform=sin}
+        \draw (0,0) node[ground]{} to [vsourcesin, l={Fn}] ++(0,4) -- ++(2,0) to [american inductor, l={$100 \ \text{mH}$}] ++(0,-2) coordinate (vr) to [R, l={$47 \ \Omega$}] ++(0,-2) node[ground]{};
+        \draw (vr) to [short, *-] ++(2,0) to [short, -*] ++(0,0.5) node[oscopeshape,anchor=in 1](os){$V_R$} (os.in 2) to [short, *-] ++(0,-0.5) node[ground]{};
+    \end{circuitikz}
+    \caption{Circuit Diagram for Experiment 2-2}
+    \label{fig:exp22-cd}
+\end{figure}
+
+\subsection{実験2-3}
+
+\Cref{fig:exp23-cd}のRLC並列回路を作成し, ADALM2000のネットワークアナライザ機能を使用して回路の応答特性を測定する.
+なお, 回路中に使用した素子は$R_i$には$10 \ \text{k}\Omega$を, $R$には$100 \ \text{k}\Omega$を, $C$には1 nFを, そして$L$には100 mHのものを使用した.
+
+\begin{figure}[H]
+    \centering
+    \begin{circuitikz}
+        \draw (0,0) node[ground]{} to [vsourcesin, l={ADALM2000}] ++(0,4) to [R, l={$R_i$}] ++(4,0) coordinate (a) ++(0,-4) coordinate (b);
+        \draw (a) |- ++(-2, -1) to [R, l={$R$}] ++(0,-2) -| (b);
+        \draw (a) |- ++(0,-1) to [american inductor, l={$L$}] ++(0,-2) -| (b);
+        \draw (a) |- ++(2,-1) to [C, l={$C$}] ++(0,-2) -| (b);
+        \draw (a) ++(0,-1) node[circ]{} (b) ++(0,1) node[circ]{};
+        \draw (b) node[ground]{};
+        \draw (0,0) ++(0,4) ++(1,0) to [short, *-o] ++(0,0.5) node[above]{$1+$};
+        \draw (0,0) ++(0,4) ++(3,0) to [short, *-o] ++(0,0.5) node[above]{$2+$};
+        \draw (b) ++(0,0.25) to[short, *-o] ++(0.5,0) node[right]{$1-,\ 2-$};
+    \end{circuitikz}
+    \caption{Circuit Diagram for Experiment 2-3}
+    \label{fig:exp23-cd}
+\end{figure}

sections/a-3/exp-result.tex

@@ -0,0 +1,92 @@
+\section{実験結果}
+
+\subsection{実験1-1}
+
+\Cref{fig:exp11-res}より, 入力信号の周期を長くするにつれ充放電の様子に違いが見られた.
+特に$T_{\text{in}} = 2 \times \tau$の場合では, コンデンサは完全に充放電されなかった.
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=6cm]{./assets/a-3/RC-10kOhm-1nF-1t.png}
+        \subcaption{$T_{\text{in}} = 2 \times \tau$}
+        \label{fig:exp11-res-a}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=6cm]{./assets/a-3/RC-10kOhm-1nF-5t.png}
+        \subcaption{$T_{\text{in}} = 2 \times 5\tau$}
+        \label{fig:exp11-res-b}
+    \end{minipage}
+    \begin{minipage}[h]{0.90\textwidth}
+        \centering
+        \includegraphics[width=6cm]{./assets/a-3/RC-10kOhm-1nF-15t.png}
+        \subcaption{$T_{\text{in}} = 2 \times 15\tau$}
+        \label{fig:exp11-res-c}
+    \end{minipage}
+    \caption{Response of RC Circuit, Used $10 \ \text{k}\Omega$ Resistor and $1 \ \text{nF}$ Capacitor}
+    \label{fig:exp11-res}
+\end{figure}
+
+\subsection{実験1-2}
+
+\Cref{fig:exp12-res}より, コンデンサと似た電圧の充放電波形が得られた.
+しかし, $T_{\text{in}} = 2 \times 0.5\tau$では特殊な波形が見られた.
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=6cm]{./assets/a-3/RL-10kOhm-100mH-0.5t.png}
+        \subcaption{$T_{\text{in}} = 2 \times 0.5\tau$}
+        \label{fig:exp12-res-a}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=6cm]{./assets/a-3/RL-10kOhm-100mH.png}
+        \subcaption{$T_{\text{in}} = 2 \times 5\tau$}
+        \label{fig:exp12-res-b}
+    \end{minipage}
+    \begin{minipage}[h]{0.90\textwidth}
+        \centering
+        \includegraphics[width=6cm]{./assets/a-3/RL-10kOhm-100mH-25t.png}
+        \subcaption{$T_{\text{in}} = 2 \times 25\tau$}
+        \label{fig:exp12-res-c}
+    \end{minipage}
+    \caption{Response of RL Circuit, Used $10 \ \text{k}\Omega$ Resistor and $100 \ \text{mH}$ Inductor}
+    \label{fig:exp12-res}
+\end{figure}
+
+\subsection{実験2-1}
+
+測定範囲を通じて, インピーダンス・位相ともに一定の傾向を確認した.
+
+\begin{figure}[H]
+    \centering
+    \input{./assets/a-3/exp2-1-bode}
+    \caption{Bode Plot of RC Circuit Response}
+    \label{fig:exp21-res}
+\end{figure}
+
+\subsection{実験2-2}
+
+100 kHzから500 kHzの範囲を境にインピーダンスは減少, 位相は$180 \textdegree$変化した.
+
+\begin{figure}[H]
+    \centering
+    \input{./assets/a-3/exp2-2-bode}
+    \caption{Bode Plot of RL Circuit Response}
+    \label{fig:exp22-res}
+\end{figure}
+
+\subsection{実験2-3}
+
+ゲインは緩やかな曲線を描き, 15 kHz付近で最大となった.
+
+\begin{figure}[H]
+    \centering
+    \includegraphics[width=10cm]{./assets/a-3/100kOhm-1nF-100mH.png}
+    \caption{Bode Plot of RLC Parallel Circuit Response}
+    \label{fig:exp23-res}
+\end{figure}

sections/a-3/reflection.tex

@@ -0,0 +1,154 @@
+\section{考察}
+
+\subsection{実験1-1}
+
+時定数とはある変動を加えた系の状態が平衡に達するまでの時間の尺度である.
+この時間が短ければ信号は直ぐに平衡状態になり, 長ければ信号の変化はゆるやかとなり, 平衡状態に達するまでの時間が長くなる\supercite{brit-time_constant}.
+
+\Cref{equ:rc-v}の指数関数項の指数が-1になる時間が時定数$\tau$である, よって時定数は\cref{equ:tc-c}となる.
+\begin{equation}
+    \label{equ:tc-c}
+    \begin{split}
+        v_C(\tau) &= v_i \left(1 - e^{-\frac{\tau}{RC}}\right) = v_i \left(1 - e^{-1}\right) \\
+        \tau &= RC
+    \end{split}
+\end{equation}
+
+\Cref{equ:tc-c}から時定数は抵抗値とキャパシタンスに比例することが分かる.
+
+今回の実験では, 時定数は$10 \ \text{k}\Omega \times 1 \ \text{nF} = 10 \ \mu\text{s}$となる.
+実際に\cref{fig:exp11-res-b}では$10 \ \mu\text{s}$で$v_i$の$(1 - e^{-1})\text{倍} \approx 60\%$まで充電されている.
+
+\subsection{実験1-2}
+
+\Cref{equ:rl-v}の指数関数項の指数が-1になる時間が時定数$\tau$なので, 時定数は\cref{equ:tc-l}となる.
+\begin{equation}
+    \label{equ:tc-l}
+    \begin{split}
+        v_L(\tau) &= v_i e^{-\frac{R}{L}\tau} = v_i e^{-1} \\
+        \tau &= \frac{L}{R}
+    \end{split}
+\end{equation}
+
+\Cref{equ:tc-l}から時定数はインダクタンスに比例し, 抵抗値に反比例することが分かる.
+
+今回の実験では, 時定数は$\frac{100 \ \text{mH}}{10 \ \text{k}\Omega} = 10 \ \mu\text{s}$となる.
+実際に\cref{fig:exp12-res-b}では$10 \ \mu\text{s}$で$v_i$の$(1 - e^{-1})\text{倍} \approx 60\%$まで充電されている.
+
+\subsection{実験2-1}
+
+\Cref{fig:exp21-cd}の回路内のシャント抵抗$R$を無視するには, $R \ll \frac{1}{2\pi{}fC}$を満たす周波数領域内である必要がある.
+コンデンサのインピーダンスがシャント抵抗の$\frac{1}{100}$倍になる場合を十分小さいとみなし, 1 nFと100 $\mu$Fのコンデンサでは\cref{tab:cap-f-range}で示した範囲となった.
+
+\begin{table}[H]
+    \centering
+    \caption{Frequency Range for a Shunt Resistor being Insignificant in the Circuit}
+    \label{tab:cap-f-range}
+    \begin{tabular}{r|l}
+        \hline
+        Capacitor & Range \\
+        \hline
+        1 nF & $f < 33.9 \ \text{kHz}$ \\
+        100 $\mu$F & $f < 0.338 \ \text{Hz}$ \\
+        \hline
+    \end{tabular}
+\end{table}
+
+\cref{tab:cap-f-range}から分かるように, 100 $\mu$Fでは計測範囲の下限1 kHzより更に低い周波数でシャント抵抗の抵抗成分が主となるため, 実験結果\cref{fig:exp21-res}の100 $\mu$Fのインピーダンスは一定となり, 電流と電圧は同相を示す理由に説明がつく. なので, 結果からこのコンデンサの静電容量の推定は不可能となる.
+
+一方, 1 nFのコンデンサは計測範囲内に納まっているので結果から静電容量の推定が可能である.
+実験結果\cref{fig:exp21-res}から, 目測できる範囲で計算すると\cref{equ:calc-capacitance-1nf}となる.
+\begin{equation}
+    \label{equ:calc-capacitance-1nf}
+    \begin{split}
+        f &= 5 \ \text{kHz} \\
+        Z &= \frac{1}{2\pi{}fC} \approx 3 \times 10^4 \\
+        C &= \frac{1}{2\pi{}fZ} \approx 1.061 \ \text{nF}
+    \end{split}
+\end{equation}
+これは定格容量の$+6.1\%$の誤差となる.
+
+\subsection{実験2-2}
+
+実験結果\cref{fig:exp22-res}より, 目測できる範囲でインダクタンスを計算すると\cref{equ:calc-inductance-100mh}となる.
+\begin{equation}
+    \label{equ:calc-inductance-100mh}
+    \begin{split}
+        f &= 5 \ \text{kHz} \\
+        Z &= 2\pi{}fL \approx 3 \times 10^3 \\
+        L &= \frac{Z}{2\pi{}f} \approx 95.49 \ \text{mH}
+    \end{split}
+\end{equation}
+これは定格インダクタンスの$-4.51\%$の誤差となる.
+
+また実験結果より, 100 kHzから500 kHzの間でインピーダンスが減少する傾向に転じた. また, 位相では180度増加した.
+この現象は現実のインダクターはRLC並列回路の一種であるとすれば説明できる.
+銅線は値が低くとも抵抗値を持ち, 巻かれているので使用する長さも長くなり抵抗値が増える.
+また, 巻線間のピッチが短くなるので銅線どうしでコンデンサのように振舞うことがある.
+この仮想的なコンデンサが持つ静電容量を寄生キャパシタンスという.
+
+マルチメータで測定したインダクターの端子間抵抗値は138 $\Omega$であったので等価回路は\cref{equ:l-equivalent-cd}となる.
+\begin{figure}[tbh]
+    \centering
+    \begin{circuitikz}
+        \draw (0,0) to[R={$138 \ \Omega$}, o-*] ++(2,0) coordinate (p);
+        \draw (p) -- ++(0,1) to[american inductor={$100 \ \text{mH}$}] ++(2,0) -- ++(0,-1);
+        \draw (p) -- ++(0,-1) to[C={$C$}] ++(2,0) -- ++(0,1);
+        \draw (p) ++(2,0) to[short, *-o] ++(1,0);
+    \end{circuitikz}
+    \caption{Equivalent Circuit of Inductor}
+    \label{equ:l-equivalent-cd}
+\end{figure}
+
+この回路のインピーダンスは\cref{equ:r-lc-z}となり, 共振周波数は\cref{equ:resfreq-r-lc}となる.
+\begin{equation}
+    \label{equ:r-lc-z}
+    \dot{Z} = R + \frac{1}{j\omega{}C + \frac{1}{j\omega{}L}} = R - j\frac{\omega{}L}{\omega{}^{2}CL - 1}
+\end{equation}
+\begin{equation}
+    \label{equ:resfreq-r-lc}
+    \begin{split}
+        Z &= |\dot{Z}| = \sqrt{R^2 + \left(\frac{\omega{}L}{\omega{}^{2}CL - 1}\right)^{2}} \\
+        Z_\text{max} &= Z(f_a) = \infty \\
+        0 &= \omega{}^{2}LC - 1 \\
+        \omega{}^{2} &= \frac{1}{LC} \\
+        \omega{} &= \frac{1}{\sqrt{LC}} = 2\pi{}f_a \\
+        f_a &= \frac{1}{2\pi{}\sqrt{LC}}
+    \end{split}
+\end{equation}
+
+$100 \ \text{kHz} < f_a < 500 \ \text{kHz}$を満たす寄生キャパシタンスは$1.061 \ \text{pF} < C < 26.53 \ \text{pF}$となる.
+また, $f_a$を\\中間の300 kHzとすると寄生キャパシタンスは2.947 pFとなる.
+
+この共振周波数を境に回路が誘導性を示すか容量性を示すかが決まってくる. 今回の実験では共振周波数より低い周波数では回路は誘導性を示し, 電流は電圧より90\textdegree 遅れ, 共振周波数より高い周波数では回路は容量性を示し, 電流は電圧より90\textdegree 進む.
+
+\subsection{実験2-3}
+
+今回の実験のパラメータから, 抵抗成分は信号抵抗と主抵抗の合成並列抵抗であることに注意して計算すると, 共振周波数は\cref{equ:res-f-exp23}となり, Q値は\cref{equ:qf-exp23}となった.
+\begin{equation}
+    \label{equ:res-f-exp23}
+    f_r = \frac{1}{2\pi\sqrt{100 \ \text{mH} \times 1 \ \text{nF}}} = 15.915 \ \text{kHz}
+\end{equation}
+\begin{equation}
+    \label{equ:qf-exp23}
+    \begin{split}
+        r &= \frac{1}{R^{-1} + {R_i}^{-1}} \approx 9090.91 \ \Omega \\
+        Q &= r \times \sqrt{\frac{1 \ \text{nF}}{100 \ \text{mH}}} = 0.9091
+    \end{split}
+\end{equation}
+そして, これらの値から半値幅の理論値を計算すると\cref{equ:bw-exp23-theory}となる.
+\begin{equation}
+    \label{equ:bw-exp23-theory}
+    \text{BW}_{\text{theory}} = \frac{f_r}{Q} \approx 17.51 \ \text{kHz}
+\end{equation}
+
+実験結果\Cref{fig:exp23-res}から目測で周波数を読み, 半値幅を概算すると\cref{equ:bw-exp23-measured}となる.
+\begin{equation}
+    \label{equ:bw-exp23-measured}
+    \text{BW} = f_2 - f_1 = 26 \ \text{kHz} - 9 \ \text{kHz} = 17 \ \text{kHz}
+\end{equation}
+
+詳細な周波数を取得していなかったので500 Hz以上の誤差が出てしまったが, 共振周波数・半値幅ともに理論値とおおかた一致した.
+
+これら共振周波数, Q値や半値幅はフィルタ回路の設計で, どの周波数の信号をどれだけの振幅で通過させるかを決定するのに重要な指標である.
+共振周波数は通過・遮断させる主な周波数を, 半値幅はフィルタの有効周波数の範囲を, そしてQ値はフィルタ通過後の振幅を決定する.

sections/a-3/theory.tex

@@ -0,0 +1,167 @@
+\section{理論}
+
+\subsection{コンデンサ}
+
+コンデンサとは電圧を加えると電荷を保持する素子である.
+コンデンサは電圧$v(t)$に比例して電流$i(t)$の時間微分である電荷$q(t)$を保持するので\cref{equ:cap-i}が成り立つ.
+\begin{equation}
+    \label{equ:cap-i}
+    \frac{dq}{dt} = i(t) = C \frac{dv}{dt}
+\end{equation}
+\Cref{equ:cap-i}を電圧$v(t)$で示すと\cref{equ:cap-v}が得られる.
+\begin{equation}
+    \label{equ:cap-v}
+    v(t) = \frac{1}{C} \int^{t}_{0} i(\delta)d\delta
+\end{equation}
+ここで, $C$はコンデンサの容量を表す\supercite{ac-theory:impedance}.
+
+抵抗器とコンデンサの直列回路をRC回路という.
+この回路の時刻$t$における電圧を考える.
+抵抗値$R$を持つ抵抗器と容量$C$を持つコンデンサの直列回路に電流$i(t)$を流した際の回路全体の電圧$v(t)$は\cref{equ:rc-v-1}となる.
+\begin{equation}
+    \label{equ:rc-v-1}
+    v(t) = Ri(t) + \frac{1}{C}\int^{t}_{0}i(\delta)d\delta
+\end{equation}
+
+ここで, \cref{equ:cap-i}を用いて\cref{equ:rc-v-1}を書き換えると一階線形微分方程式\cref{equ:rc-v-2}を得る.
+\begin{equation}
+    \label{equ:rc-v-2}
+    v_i = RC\frac{d v_{C}}{dt} + v_{C}(t)
+\end{equation}
+\Cref{equ:rc-v-2}の入力電圧$v_i$は直流電圧で任意の定数とする.
+
+\Cref{equ:rc-v-2}の微分方程式を変数分離形として一般解を求めると\cref{equ:rc-v-solv}となる.
+\begin{equation}
+    \label{equ:rc-v-solv}
+    \begin{aligned}
+        RC\frac{d v_{C}}{dt} &= v_i - v_{C} \\
+        \frac{d v_{C}}{v_i - v_{C}} &= \frac{1}{RC} dt \\
+        \int \frac{d v_{C}}{v_i - v_{C}} &= \int \frac{1}{RC} dt \\
+        \log{(v_i - v_C)} + C_v &= -\frac{t}{RC} + C_t \\
+        e^{C_v}(v_i - v_C) &= e^{C_t} e^{-\frac{t}{RC}} \\
+        v_C &= v_i - \left(e^{C_t - C_v}\right) e^{-\frac{t}{RC}}
+    \end{aligned}
+\end{equation}
+
+ここで$e^{C_t - C_v}$を$C_0$と置き, $v_{C}(0) = 0$という条件を満たす$C_0$を与えると\cref{equ:rc-v}となる.
+\begin{align}
+    \label{equ:rc-v}
+    v_C(t) = v_i - C_{0}e^{-\frac{t}{RC}} = v_i\left(1 - e^{-\frac{t}{RC}}\right) && \text{where, } \ C_0 = v_i
+\end{align}
+
+
+\subsection{インダクタ}
+
+インダクタは電流を磁束としてエネルギーを保持する素子である.
+磁束が電流$i(t)$に比例する場合のインダクタにかかる電圧は\cref{equ:l-v}で示される.
+\begin{equation}
+    \label{equ:l-v}
+    v(t) = L\frac{di}{dt}
+\end{equation}
+ここで, $L$はインダクタンスを表す\supercite{ac-theory:impedance}.
+
+抵抗器とインダクタの直列回路をRL回路という. この回路の時刻$t$における電圧を考える.
+抵抗値$R$を持つ抵抗器とインダクタンス$L$を持つインダクタの直列回路に電流$i(t)$を流した際の回路全体の電圧$v(t)$は\cref{equ:rl-v-1}となる.
+\begin{equation}
+    \label{equ:rl-v-1}
+    v(t) = Ri(t) + L\frac{di}{dt}
+\end{equation}
+
+\Cref{equ:rl-v-1}の$v(t)$を直流電圧$v_i$の任意の定数関数とすると\cref{equ:rl-v-2}の一階微分方程式が得られる.
+\begin{equation}
+    \label{equ:rl-v-2}
+    v_i = Ri + L\frac{di}{dt}
+\end{equation}
+
+\Cref{equ:rl-v-2}の微分方程式を変数分離形として一般解を求めると\cref{equ:rl-v-solv}となる.
+\begin{equation}
+    \label{equ:rl-v-solv}
+    \begin{aligned}
+        L\frac{di}{dt} &= v_i - Ri = v_L \\
+        \frac{di}{v_i - Ri} &= \frac{dt}{L} \\
+        \int \frac{di}{v_i - Ri} &= \int \frac{dt}{L} \\
+        -\frac{1}{R}\log{(v_i - Ri)} + C_i &= \frac{1}{L}t + C_t \\
+        \log{(v_i - Ri)} + C_i &= -\frac{R}{L}t + C_t \\
+        e^{C_i}(v_i - Ri) &= e^{C_t}e^{-\frac{R}{L}t} \\
+        v_i - Ri &= e^{C_t - C_i}e^{-\frac{R}{L}t} = v_L \\
+        i &= \frac{v_i}{R} - \frac{1}{R}e^{C_t - C_i}e^{-\frac{R}{L}t}
+    \end{aligned}
+\end{equation}
+ここで, $e^{C_t - C_i}$を$C_0$とし, $i(0) = 0$という条件を満たす$C_0$を与えると\cref{equ:rl-v}となる.
+\begin{align}
+    \label{equ:rl-i} i(t) &= \frac{v_i}{R} - \frac{C_0}{R}e^{-\frac{R}{L}t} = \frac{v_i}{R}\left(1 - e^{-\frac{R}{L}t}\right) && \text{where, } \ C_0 = v_i \\
+    \label{equ:rl-v} v_{L}(t) &= C_0 e^{-\frac{R}{L}t} = v_i e^{-\frac{R}{L}t} && \text{where, } \ C_0 = v_i
+\end{align}
+
+\subsection{共振周波数・Q値・半値幅}
+
+RLCの交流回路網でインピーダンスが純抵抗性・純コンダクタンスを示す時の周波数を共振周波数という.
+
+直列回路の場合, インピーダンスは\cref{equ:rlc-s-z}となる.
+\begin{equation}
+    \label{equ:rlc-s-z}
+    Z = \sqrt{R^2 + \left(\omega{}L - \frac{1}{\omega{}C}\right)^2}
+\end{equation}
+このインピーダンスが純抵抗性を示すのは括弧内の値が0になれば良いので共振周波数$f_r$は\cref{equ:rlc-s-fr}となる\supercite{ac-theory:impedance}.
+\begin{equation}
+    \label{equ:rlc-s-fr}
+    f_r = \frac{\omega{}_r}{2\pi} = \frac{1}{2\pi{}\sqrt{LC}}
+\end{equation}
+
+並列回路の場合, アドミタンスは\cref{equ:rlc-p-z}となる.
+\begin{equation}
+    \label{equ:rlc-p-z}
+    Y = \sqrt{\frac{1}{R^2} + \left(\omega{}C - \frac{1}{\omega{}L}\right)^2}
+\end{equation}
+このアドミタンスが純コンダクタンス性を示すのは括弧内の値が0になれば良いので共振周波数$f_a$は\cref{equ:rlc-p-fa}となる\supercite{ac-theory:rlc-parallel}.
+\begin{equation}
+    \label{equ:rlc-p-fa}
+    f_a = \frac{\omega{}_a}{2\pi} = \frac{1}{2\pi\sqrt{LC}}
+\end{equation}
+
+Q値とはQuality Factorのことで, 共振時の共振のよさを示す指標である.
+直列回路ではインダクタのインピーダンスと抵抗器の抵抗値との比がコンデンサのインピーダンスと抵抗器の抵抗値との比が等しい時の値で,
+並列回路ではインダクタのアドミタンスと抵抗器のコンダクタンスとの比がコンデンサのアドミタンスと抵抗器のコンダクタンスとの比が等しい時の値である\supercite{ac-theory:impedance}\supercite{ac-theory:rlc-parallel}.
+\begin{equation}
+    \label{equ:q-factor-s}
+    Q_{\text{Series}} = \frac{\omega{}_r L}{R} = \frac{1}{\omega{}_r CR} = \frac{1}{R} \frac{L}{\sqrt{LC}} = \frac{1}{R} \frac{\sqrt{LC}}{C} = \frac{1}{R}\sqrt{\frac{L}{C}}
+\end{equation}
+\begin{equation}
+    \label{equ:q-factor-p}
+    Q_{\text{Parallel}} = \omega{}_a CR = \frac{R}{\omega{}_a L} = R \frac{C}{\sqrt{LC}} = R \frac{\sqrt{LC}}{L} = R \sqrt{\frac{C}{L}}
+\end{equation}
+
+半値幅とは共振周波数を中心に電力が半分, または電流・電圧のゲインが$\frac{1}{\sqrt{2}}$倍になる2つの周波数の差を表す値で, 共振が鋭ければ鋭いほどこの値は小さくなる.
+直列回路の場合, 半値幅BWは\cref{equ:bw-s}となる\supercite{ac-theory:impedance}.
+\begin{equation}
+    \label{equ:bw-s}
+    \begin{split}
+        Z_r &= R \\
+        \sqrt{2}Z_r &= \sqrt{R^2 + \left(\omega{}L - \frac{1}{\omega{}C}\right)^2} \\
+        2{Z_r}^2 &= 2R^2 = R^2 + \left(\omega{}L - \frac{1}{\omega{}C}\right)^2 \\
+        \pm{}R &= \left(\omega{}L - \frac{1}{\omega{}C}\right) = \frac{\omega{}^{2}LC - 1}{\omega{}C} \\
+        0 &= \omega{}^{2}LC \pm \omega{}RC - 1, (\omega{} > 0) \\
+        \omega{} &= \frac{\pm{}RC + \sqrt{D}}{2LC} \\
+        \omega{}_1 &= \frac{-RC + \sqrt{D}}{2LC} \\
+        \omega{}_2 &= \frac{RC + \sqrt{D}}{2LC} \\
+        \text{BW} &= f_2 - f_1 = \frac{\omega{}_2}{2\pi} - \frac{\omega{}_1}{2\pi} = \frac{R}{2\pi{}L} = \frac{f_r}{Q_{\text{Series}}}
+    \end{split}
+\end{equation}
+
+\newpage
+
+並列回路の場合, 半値幅BWは\cref{equ:bw-p}となる\supercite{ac-theory:rlc-parallel}.
+\begin{equation}
+    \label{equ:bw-p}
+    \begin{split}
+        Y_r &= \frac{1}{R} = G \\
+        \sqrt{2}Y_r &= \sqrt{G^2 + \left(\omega{}C - \frac{1}{\omega{}L}\right)^2} \\
+        2{Y_r}^2 &= 2G^2 = G^2 + \left(\omega{}C - \frac{1}{\omega{}L}\right)^2 \\
+        \pm{}G &= \frac{\omega{}^{2}LC - 1}{\omega{}L} \\
+        0 &= \omega{}^{2}LC \pm \omega{}LG - 1, (\omega{} > 0) \\
+        \omega{} &= \frac{\pm{}LG + \sqrt{D}}{2LC} \\
+        \omega{}_1 &= \frac{-LG + \sqrt{D}}{2LC} \\
+        \omega{}_2 &= \frac{LG + \sqrt{D}}{2LC} \\
+        \text{BW} &= f_2 - f_1 = \frac{\omega{}_2}{2\pi} - \frac{\omega{}_1}{2\pi} = \frac{G}{2\pi{}C} = \frac{1}{2\pi{}RC} = \frac{f_a}{Q_{\text{Parallel}}}
+    \end{split}
+\end{equation}

sections/t-2/exp-detail.tex

@@ -0,0 +1,247 @@
+\section{実験手順・条件}
+
+\subsection{実験器具}
+
+\begin{itemize}
+    \item{ブレッドボード}
+    \item{直流安定化電源}
+    \item{タクトスイッチ x4}
+    \item{LED x4}
+    \item{7セグメント LED}
+    \item{カーボン抵抗器 $330 \Omega$ or $470 \Omega$ x12}
+    \item{ジャンパーワイヤ}
+    \item{ANDゲートIC TC74HC08}
+    \item{NANDゲートIC HD14012BP}
+    \item{ORゲートIC TC74HC32}
+    \item{NOTゲートIC TC74HC04}
+    \item{7セグメントドライバIC TC4511}
+    \item{DフリップフロップIC TC74HC74 x2}
+    \item{Nch MOSFET}
+\end{itemize}
+
+\subsection{課題1-1}
+
+ANDゲートあるいはORゲートの動作を確認する.
+
+2つのボタンを入力とし, 出力を7セグメントLEDのドットに表示させる回路を作成する.
+
+\subsection{課題1-2}
+
+4入力NANDゲートの動作を確認する.
+
+4つのボタンを入力とし, 出力を7セグメントLEDのドットに表示させる回路を作成する.
+
+\subsection{課題1-3}
+
+\cref{fig:a1-3-cd}に示す組み合わせ回路を作成し動作を確認する.
+
+4つのボタンを入力とし, 出力を7セグメントLEDのドットに表示させる回路を作成する.
+
+\begin{figure}[H]
+    \centering
+    \begin{circuitikz}[scale=0.75]
+        \ctikzset{logic ports=ieee}
+        \ctikzset{logic ports/scale=0.75}
+        \node (A) at (0,2) {$A_{\text{IN}}$};
+        \node (B) at (0,1) {$B_{\text{IN}}$};
+        \node (C) at (0,0) {$C_{\text{IN}}$};
+        \node (D) at (0,-1) {$D_{\text{IN}}$};
+
+        \draw (2,1.5) node[and port](a){};
+        \draw (2,-0.5) node[and port](b){};
+        \draw (4.5,0.5) node[and port](c){};
+
+        \draw (A) -| (a.in 1) (B) -| (a.in 2);
+        \draw (C) -| (b.in 1) (D) -| (b.in 2);
+        \draw (a.out) -| (c.in 1) (b.out) -| (c.in 2);
+        \draw (c.out) -- ++(0.5,0) node[right] {$D_p$};
+    \end{circuitikz}
+    \caption{Circuit Diagram of Assignment 1-3}
+    \label{fig:a1-3-cd}
+\end{figure}
+
+\subsection{課題1-4}
+
+\cref{fig:a1-4-cd}に示す組み合わせ回路を作成し動作を確認する.
+
+4つのボタンを入力とし, 出力を7セグメントLEDのドットに表示させる回路を作成する.
+
+\begin{figure}[H]
+    \centering
+    \begin{circuitikz}[scale=0.75]
+        \ctikzset{logic ports=ieee}
+        \ctikzset{logic ports/scale=0.75}
+        \node (A) at (0,2) {$A_{\text{IN}}$};
+        \node (B) at (0,1) {$B_{\text{IN}}$};
+        \node (C) at (0,0) {$C_{\text{IN}}$};
+        \node (D) at (0,-1) {$D_{\text{IN}}$};
+
+        \draw (2,1.5) node[and port](a){};
+        \draw (2,-0.5) node[and port](b){};
+        \draw (4.5,0.5) node[and port](c){};
+        \draw (6.5,0.5) node[not port](d){};
+
+        \draw (A) -| (a.in 1) (B) -| (a.in 2);
+        \draw (C) -| (b.in 1) (D) -| (b.in 2);
+        \draw (a.out) -| (c.in 1) (b.out) -| (c.in 2);
+        \draw (c.out) -- (d.in);
+        \draw (d.out) -- ++(0.5,0) node[right] {$D_p$};
+    \end{circuitikz}
+    \caption{Circuit Diagram of Assignment 1-4}
+    \label{fig:a1-4-cd}
+\end{figure}
+
+\subsection{課題2-1}
+
+7セグメントドライバICを用いて1桁のBDCデコーダを作成する.
+
+\subsection{課題2-2B}
+
+論理ゲートを複数個使用し, 0-9以外の数の表現を実現する回路を作成する.
+なお, 既存の0-9に対応するBDCコードが入力された際にはセグメントを点灯させないこと.
+
+\subsection{課題3-1}
+
+論理ゲートを組み合わせて\cref{fig:a3-1-cd}のRSフリップフロップを作成し, 動作を確認する.
+
+\begin{figure}[H]
+    \centering
+    \begin{circuitikz}[scale=0.75]
+        \ctikzset{logic ports=ieee}
+        \ctikzset{logic ports/scale=0.75}
+        \ctikzset{diodes/scale=0.5}
+        \ctikzset{resistors/scale=0.5}
+        \ctikzset{switches/scale=0.75}
+
+        \node [or port] at (0,1.5) (or1){};
+        \node [or port] at (0,-1.5) (or2){};
+        \node [not port] at (3,1.5) (not1){};
+        \node [not port] at (3,-1.5) (not2){};
+
+        \draw (or1.out) -- (not1.in) (or2.out) -- (not2.in);
+        \draw (not1.out) -- ++(1,0) to [short, *-] ++(0,-0.5) coordinate(p1);
+        \draw (not2.out) -- ++(1,0) to [short, *-] ++(0,0.5) coordinate(p2);
+        \draw (or1.in 2) -- ++(0,-0.5) coordinate (p3);
+        \draw (or2.in 1) -- ++(0,0.5) coordinate (p4);
+        \draw (p1) -- (p4) (p2) -- (p3);
+        \draw ($(not1.out) + (1,0)$) -- ++(4,0) -- ++(0,-2) to[leDo, l={$D_D$}] ++(0,-1) to[R, l={$330 \ \Omega$}] ++(0,-1) node[ground]{};
+        \draw ($(not2.out) + (1,0)$) -- ++(1,0) -- ++(0,2) -- ++(1,0)  -- ++(0,-1) to[leDo, l={$D_C$}] ++(0,-1) to[R, l={$330 \ \Omega$}] ++(0,-1) node[ground]{};
+
+        \draw (-8,3) node[vcc]{$V_{DD}$} -- ++(0,-1.5) coordinate (v);
+        \draw (v) to [normal open switch] ++(4,0) coordinate (in1) -- ++(0.5,0) |- (or1.in 1) (in1) to [short, *-] ++(0,-2) to [leDo, l={$D_B$}] ++(0,-1) to [R, l={$330 \ \Omega$}] ++(0,-1) node[ground]{};
+        \draw (v) -- ++(0,-1) to [normal open switch] ++(1.5,0) coordinate (in2) -- ++(0.5,0) -| ($(or2.in 2) + (-0.5,0)$) -- (or2.in 2) (in2) to [short, *-] ++(0,-1) to [leDo, l={$D_A$}] ++(0,-1) to [R, l={$330 \ \Omega$}] ++(0,-1) node[ground]{};
+    \end{circuitikz}
+    \caption{Circuit Diagram of Assignment 3-1}
+    \label{fig:a3-1-cd}
+\end{figure}
+
+\subsection{課題3-2}
+
+DフリップフロップICを用いて\cref{fig:a3-2-cd}の回路を作成し, 動作を確認する.
+
+\begin{figure}[H]
+    \centering
+    \begin{circuitikz}[scale=0.9]
+        \ctikzset{logic ports=ieee}
+        \ctikzset{flipflops/scale=0.75}
+        \ctikzset{resistors/scale=0.75}
+        \ctikzset{diodes/scale=0.75}
+        \node [flipflop D] at (0,0) (Df){};
+        
+        \draw (-2.5,2) node[vcc]{$V_{DD}$} -- ++(0,-0.5) to[normal open switch] ++(0,-1.5) coordinate(x) to[leDo, l={$D_p$}] ++(0,-2) to[R={$330 \Omega$}] ++(0,-2) node[ground]{};
+        \draw (x) to[short,o-] ++(1,0) |- (Df.pin 3);
+        \draw (Df.pin 4) -- ++(0.5,0) -- ++(0,2) -- ++(-2.5,0) |- (Df.pin 1);
+        \draw (Df.pin 6) -- ++(1.5,0) to[leDo, l={$D_A$}] ++(0,-2.5) to[R={$330 \Omega$}] ++(0,-2) node[ground]{};
+    \end{circuitikz}
+    \caption{Circuit Diagram of Assignment 3-2}
+    \label{fig:a3-2-cd}
+\end{figure}
+
+\subsection{課題3-3}\label{sec:a3-3}
+
+DフリップフロップICを2個用いて\cref{fig:a3-3-cd}の順列回路を作成し, 動作を確認する.
+
+\begin{figure}[H]
+    \centering
+    \begin{circuitikz}
+        \ctikzset{logic ports=ieee}
+        \ctikzset{flipflops/scale=0.75}
+        \ctikzset{resistors/scale=0.75}
+        \ctikzset{diodes/scale=0.75}
+        %\ctikzset{multipoles/flipflop/font=\tiny}
+        \ctikzset{multipoles/flipflop/pin spacing=0.5}
+
+        \node [flipflop D] at (0,0) (Df0){};
+        \node [flipflop D] at (3,0) (Df1){};
+        \node [flipflop D] at (6,0) (Df2){};
+        \node [flipflop D] at (9,0) (Df3){};
+
+        \draw (-2,2) node[vcc]{$V_{DD}$} to[normal open switch, -*] ++(0,-2) coordinate (x) to[leDo, l_={$D_p$}] ++(0,-1.5) to[R, l_={$330 \Omega$}] ++(0,-1.5) node[ground]{};
+        \draw (x) -- ++(0.75,0) |- (Df0.pin 3);
+        \draw (Df0.pin 4) -- ++(0.25,0) -- ++(0,2) -- ++(-2.25,0) |- (Df0.pin 1);
+        \draw (Df1.pin 4) -- ++(0.25,0) -- ++(0,2) -- ++(-2.25,0) |- (Df1.pin 1);
+        \draw (Df2.pin 4) -- ++(0.25,0) -- ++(0,2) -- ++(-2.25,0) |- (Df2.pin 1);
+        \draw (Df3.pin 4) -- ++(0.25,0) -- ++(0,2) -- ++(-2.25,0) |- (Df3.pin 1);
+
+        \draw (Df0.pin 6) -- ++(0.75,0) to[short,-*] ++(0,-0.75) coordinate (ck1) to[leDo, l_={$D_A$}] ++(0,-1.25) to[R, l_={$330 \Omega$}] ++(0,-1.5) node[ground]{};
+        \draw (ck1) -| (Df1.pin 3);
+        \draw (Df1.pin 6) -- ++(0.75,0) to[short,-*] ++(0,-0.75) coordinate (ck2) to[leDo, l_={$D_B$}] ++(0,-1.25) to[R, l_={$330 \Omega$}] ++(0,-1.5) node[ground]{};
+        \draw (ck2) -| (Df2.pin 3);
+        \draw (Df2.pin 6) -- ++(0.75,0) to[short,-*] ++(0,-0.75) coordinate (ck3) to[leDo, l_={$D_C$}] ++(0,-1.25) to[R, l_={$330 \Omega$}] ++(0,-1.5) node[ground]{};
+        \draw (ck3) -| (Df3.pin 3);
+        \draw (Df3.pin 6) -- ++(0.75,0) -- ++(0,-0.75) to[leDo, l_={$D_D$}] ++(0,-1.25) to[R, l_={$330 \Omega$}] ++(0,-1.5) node[ground]{};
+    \end{circuitikz}
+    \caption{Circuit Diagram of Assignment 3-3}
+    \label{fig:a3-3-cd}
+\end{figure}
+
+\subsection{課題3-4}
+
+\cref{fig:a3-4-cd}の順序回路を組み, 動作を確認する. ? に適切な論理ゲートを使用する.
+
+\begin{figure}[H]
+    \centering
+    \begin{circuitikz}
+        \ctikzset{logic ports=ieee}
+        \ctikzset{logic ports/scale=0.75}
+        \ctikzset{flipflops/scale=0.75}
+        \ctikzset{resistors/scale=0.75}
+        \ctikzset{diodes/scale=0.75}
+        %\ctikzset{multipoles/flipflop/font=\tiny}
+        \ctikzset{multipoles/flipflop/pin spacing=0.5}
+
+        \node [flipflop D] at (0,0) (Df0){};
+        \node [flipflop D] at (3,0) (Df1){};
+        \node [flipflop D] at (6,0) (Df2){};
+        \node [flipflop D] at (9,0) (Df3){};
+        \node [european blank port] at ($(Df0.pin 3) - (0.25,0)$) (ckGate) {?};
+        \node [nand port, number inputs=4, rotate=180] at ($(Df0) + (0,4)$) (nandGate) {};
+
+        \draw (nandGate.out) -| (ckGate.in 1);
+
+        \draw (-3.5,2) node[vcc]{$V_{DD}$} to[normal open switch, -*] ++(0,-2) coordinate (x) to[leDo, l_={$D_p$}] ++(0,-1.5) to[R, l_={$330 \Omega$}] ++(0,-1.5) node[ground]{};
+        \draw (x) -- ++(0.75,0) |- (ckGate.in 2) (ckGate.out) -- (Df0.pin 3);
+        \draw (Df0.pin 4) -- ++(0.25,0) -- ++(0,2) -- ++(-2.25,0) |- (Df0.pin 1);
+        \draw (Df1.pin 4) -- ++(0.25,0) -- ++(0,2) -- ++(-2.25,0) |- (Df1.pin 1);
+        \draw (Df2.pin 4) -- ++(0.25,0) -- ++(0,2) -- ++(-2.25,0) |- (Df2.pin 1);
+        \draw (Df3.pin 4) -- ++(0.25,0) -- ++(0,2) -- ++(-2.25,0) |- (Df3.pin 1);
+
+        \draw (Df0.pin 6) to[short,-*] ++(0.75,0) coordinate (AIN) to[short,-*] ++(0,-0.75) coordinate (ck1) to[leDo, l_={$D_A$}] ++(0,-1.25) to[R, l_={$330 \Omega$}] ++(0,-1.5) node[ground]{};
+        \draw (ck1) -| (Df1.pin 3);
+        \draw (AIN) |- (nandGate.in 1);
+        \draw (Df1.pin 6) to[short,-*] ++(0.75,0) coordinate (BIN) to[short,-*] ++(0,-0.75) coordinate (ck2) to[leDo, l_={$D_B$}] ++(0,-1.25) to[R, l_={$330 \Omega$}] ++(0,-1.5) node[ground]{};
+        \draw (ck2) -| (Df2.pin 3);
+        \draw ($(BIN) + (0,2)$) node[not port, rotate=90](n1){} (BIN) -- (n1.in) (n1.out) |- (nandGate.in 2);
+        \draw (Df2.pin 6) to[short,-*] ++(0.75,0) coordinate (CIN) to[short,-*] ++(0,-0.75) coordinate (ck3) to[leDo, l_={$D_C$}] ++(0,-1.25) to[R, l_={$330 \Omega$}] ++(0,-1.5) node[ground]{};
+        \draw (ck3) -| (Df3.pin 3);
+        \draw ($(CIN) + (0,2)$) node[not port, rotate=90](n2){} (CIN) -- (n2.in) (n2.out) |- (nandGate.in 3);
+        \draw (Df3.pin 6) to[short,-*] ++(0.75,0) coordinate (DIN) -- ++(0,-0.75) to[leDo, l_={$D_D$}] ++(0,-1.25) to[R, l_={$330 \Omega$}] ++(0,-1.5) node[ground]{};
+        \draw (DIN) |- (nandGate.in 4);
+    \end{circuitikz}
+    \caption{Circuit Diagram of Assignment 3-4}
+    \label{fig:a3-4-cd}
+\end{figure}
+
+\subsection{応用課題 A}
+
+\Cref{sec:a3-3}で作成した4ビットカウンタにおいて, 最下位ビットのDフリップフロップのCKにパルスを印加した瞬間のそれぞれのビット出力の応答波形を観察する.

sections/t-2/exp-result.tex

@@ -0,0 +1,571 @@
+\section{実験結果}
+
+\subsection{課題 1-1}
+
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/and-gate/state-00.jpg}
+        \subcaption{$a = 0, \ b = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/and-gate/state-01.jpg}
+        \subcaption{$a = 1, \ b = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/and-gate/state-11.jpg}
+        \subcaption{$a = 1, \ b = 1$}
+    \end{minipage}
+    \caption{74HC08 AND Gate, Input A on Second from Right ($x = a \cdot b$)}
+    \label{fig:a1-1-res}
+\end{figure}
+
+\subsubsection{観測された真理値表}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed Truth Table of $x = a \cdot b$}
+    \label{tab:a1-1-res-tt}
+    \begin{tabular}{ccc}
+        \hline
+        a & b & $x$ \\
+        \hline
+        0 & 0 & 0 \\
+        1 & 0 & 0 \\
+        0 & 1 & 0 \\
+        1 & 1 & 1 \\
+        \hline
+    \end{tabular}
+\end{table}
+
+\subsection{課題 1-2}
+
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/nand-4/state-0000.jpg}
+        \subcaption{$a = 0, \ b = 0, \ c = 0, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/nand-4/state-0011.jpg}
+        \subcaption{$a = 1, \ b = 1, \ c = 0, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/nand-4/state-1111.jpg}
+        \subcaption{$a = 1, \ b = 1, \ c = 1, \ d = 1$}
+    \end{minipage}
+    \caption{HD14012BP 4 Inputs NAND Gate ($x = \overline{a \cdot b \cdot c \cdot d}$)}
+    \label{fig:a1-2-res}
+\end{figure}
+
+\subsubsection{観測された真理値表}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed Truth Table of $x = \overline{a \cdot b \cdot c \cdot d}$}
+    \label{tab:a1-2-res-tt}
+    \begin{tabular}{ccccc}
+        \hline
+        a & b & c & d & x \\
+        \hline
+        0 & 0 & 0 & 0 & 1 \\
+        1 & 0 & 0 & 0 & 1 \\
+        0 & 1 & 0 & 0 & 1 \\
+        1 & 1 & 0 & 0 & 1 \\
+        0 & 0 & 1 & 0 & 1 \\
+        1 & 0 & 1 & 0 & 1 \\
+        0 & 1 & 1 & 0 & 1 \\
+        1 & 1 & 1 & 0 & 1 \\
+        0 & 0 & 0 & 1 & 1 \\
+        1 & 0 & 0 & 1 & 1 \\
+        0 & 1 & 0 & 1 & 1 \\
+        1 & 1 & 0 & 1 & 1 \\
+        0 & 0 & 1 & 1 & 1 \\
+        1 & 0 & 1 & 1 & 1 \\
+        0 & 1 & 1 & 1 & 1 \\
+        1 & 1 & 1 & 1 & 0 \\
+        \hline
+    \end{tabular}
+\end{table}
+
+\subsection{課題 1-3}
+
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/and-4/state-0000.jpg}
+        \subcaption{$a = 0, \ b = 0, \ c = 0, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/and-4/state-0010.jpg}
+        \subcaption{$a = 0, \ b = 1, \ c = 0, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/and-4/state-1111.jpg}
+        \subcaption{$a = 1, \ b = 1, \ c = 1, \ d = 1$}
+    \end{minipage}
+    \caption{
+        \parbox[t]{7.5cm}{4 Inputs AND Gate with Three 2 Inputs AND Gates, \\ Input A on Most Left ($x = (a \cdot b) \cdot (c \cdot d)$)}
+    }
+    \label{fig:a1-3-res}
+\end{figure}
+
+\subsubsection{観測された真理値表}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed Truth Table of $x = (a \cdot b) \cdot (c \cdot d)$}
+    \label{tab:a1-3-res-tt}
+    \begin{tabular}{ccccc}
+        \hline
+        a & b & c & d & x \\
+        \hline
+        0 & 0 & 0 & 0 & 0 \\
+        1 & 0 & 0 & 0 & 0 \\
+        0 & 1 & 0 & 0 & 0 \\
+        1 & 1 & 0 & 0 & 0 \\
+        0 & 0 & 1 & 0 & 0 \\
+        1 & 0 & 1 & 0 & 0 \\
+        0 & 1 & 1 & 0 & 0 \\
+        1 & 1 & 1 & 0 & 0 \\
+        0 & 0 & 0 & 1 & 0 \\
+        1 & 0 & 0 & 1 & 0 \\
+        0 & 1 & 0 & 1 & 0 \\
+        1 & 1 & 0 & 1 & 0 \\
+        0 & 0 & 1 & 1 & 0 \\
+        1 & 0 & 1 & 1 & 0 \\
+        0 & 1 & 1 & 1 & 0 \\
+        1 & 1 & 1 & 1 & 1 \\
+        \hline
+    \end{tabular}
+\end{table}
+
+\subsection{課題 1-4}
+
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/nand-from-ands/state-0000.jpg}
+        \subcaption{$a = 0, \ b = 0, \ c = 0, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/nand-from-ands/state-0101.jpg}
+        \subcaption{$a = 1, \ b = 0, \ c = 1, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/nand-from-ands/state-1111.jpg}
+        \subcaption{$a = 1, \ b = 1, \ c = 1, \ d = 1$}
+    \end{minipage}
+    \caption{
+        \parbox[t]{8cm}{4 Inputs NAND Gate with Three 2 Inputs AND Gates and \\ a NOT Gate, Input A on Most Left ($x = \overline{(a \cdot b) \cdot (c \cdot d)}$)}
+    }
+    \label{fig:a1-4-res}
+\end{figure}
+
+\subsubsection{観測された真理値表}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed Truth Table of $x = \overline{(a \cdot b) \cdot (c \cdot d)}$}
+    \label{tab:a1-4-res-tt}
+    \begin{tabular}{ccccc}
+        \hline
+        a & b & c & d & x \\
+        \hline
+        0 & 0 & 0 & 0 & 1 \\
+        1 & 0 & 0 & 0 & 1 \\
+        0 & 1 & 0 & 0 & 1 \\
+        1 & 1 & 0 & 0 & 1 \\
+        0 & 0 & 1 & 0 & 1 \\
+        1 & 0 & 1 & 0 & 1 \\
+        0 & 1 & 1 & 0 & 1 \\
+        1 & 1 & 1 & 0 & 1 \\
+        0 & 0 & 0 & 1 & 1 \\
+        1 & 0 & 0 & 1 & 1 \\
+        0 & 1 & 0 & 1 & 1 \\
+        1 & 1 & 0 & 1 & 1 \\
+        0 & 0 & 1 & 1 & 1 \\
+        1 & 0 & 1 & 1 & 1 \\
+        0 & 1 & 1 & 1 & 1 \\
+        1 & 1 & 1 & 1 & 0 \\
+        \hline
+    \end{tabular}
+\end{table}
+
+\subsection{課題 2-1}
+
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/7seg-bcd/state-0.jpg}
+        \subcaption{$a = 0, \ b = 0, \ c = 0, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/7seg-bcd/state-7.jpg}
+        \subcaption{$a = 1, \ b = 1, \ c = 1, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/7seg-bcd/invalid.jpg}
+        \subcaption{$a = 0, \ b = 1, \ c = 0, \ d = 1$}
+    \end{minipage}
+    \caption{7 Segment Driver (4 Bits BDC Input, LSB on Left)}
+    \label{fig:a2-1-res}
+\end{figure}
+
+\subsubsection{観測された真理値表}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed Truth Table of 7 Segment Driver}
+    \label{tab:a2-1-res-tt}
+    \begin{tabular}{ccccccccccc}
+        \hline
+        a & b & c & d & A & B & C & D & E & F & G \\
+        \hline
+        0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 0 \\
+        1 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 \\
+        0 & 1 & 0 & 0 & 1 & 1 & 0 & 1 & 1 & 0 & 1 \\
+        1 & 1 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 1 \\
+        0 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 1 & 1 \\
+        1 & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 \\
+        0 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 1 \\
+        1 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 0 \\
+        0 & 0 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\ 
+        1 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 1 & 1 \\
+        0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 
+        1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
+        0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
+        1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
+        0 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
+        1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
+        \hline
+    \end{tabular}
+\end{table}
+
+\subsection{課題 2-2B}
+
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-a.jpg}
+        \subcaption{$a = 0, \ b = 1, \ c = 0, \ d = 1$}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-b.jpg}
+        \subcaption{$a = 1, \ b = 1, \ c = 0, \ d = 1$}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-c.jpg}
+        \subcaption{$a = 0, \ b = 0, \ c = 1, \ d = 1$}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-d.jpg}
+        \subcaption{$a = 1, \ b = 0, \ c = 1, \ d = 1$}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-e.jpg}
+        \subcaption{$a = 0, \ b = 1, \ c = 1, \ d = 1$}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-f.jpg}
+        \subcaption{$a = 1, \ b = 1, \ c = 1, \ d = 1$}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/invalid.jpg}
+        \subcaption{$a = 1, \ b = 0, \ c = 0, \ d = 1$}
+    \end{minipage}
+    \hspace{0.45\textwidth}
+    \caption{7 Segment Hexadecimal Decoder 10-15 Only (4 Bits BCD Input, LSB on Left)}
+    \label{fig:a2-2b-res}
+\end{figure}
+
+\subsubsection{観測された真理値表}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed Truth Table of 7 Segment Hexadecimal Decoder (* Indicates Don't Care Term)}
+    \label{tab:a2-2b-res-tt}
+    \begin{tabular}{ccccccccccc}
+        \hline
+        a & b & c & d & A & B & C & D & E & F & G \\
+        \hline
+        * & * & * & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
+        * & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
+        0 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 1 & 1 \\
+        1 & 1 & 0 & 1 & 0 & 0 & 1 & 1 & 1 & 1 & 1 \\
+        0 & 0 & 1 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 \\
+        1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 1 \\
+        0 & 1 & 1 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 1 \\
+        1 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 \\
+        \hline
+    \end{tabular}
+\end{table}
+
+\subsection{課題 3-1}
+
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/rs-ff/initial.jpg}
+        \subcaption{Initial State}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/rs-ff/s-hold.jpg}
+        \subcaption{Set Hold}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/rs-ff/s-release.jpg}
+        \subcaption{Set Release}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/rs-ff/r-hold.jpg}
+        \subcaption{Reset Hold}
+    \end{minipage}
+    \caption{
+        \parbox[t]{8cm}{RS Latch with OR Gates and NOT Gates (LEDs Represent Set, Reset, Inverted Output, Output from Left)}
+    }
+    \label{fig:a3-1-res}
+\end{figure}
+
+\subsubsection{観測された挙動}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed State Transition Table of RS Latch}
+    \label{tab:a3-1-res-st}
+    \begin{tabular}{ccccl}
+        \hline
+        $R$ & $S$ & $Q$ & $\overline{Q}$ & Action \\
+        \hline
+        0 & 0 & $Q$ & $\overline{Q}$ & Hold \\
+        0 & 1 & 1 & 0 & Set \\
+        1 & 0 & 0 & 1 & Reset \\
+        1 & 1 & X & X & Unstable Behaviour \\
+        \hline
+    \end{tabular}
+\end{table}
+
+\subsection{課題 3-2}
+
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff/initial.jpg}
+        \subcaption{Initial State}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff/clk-1.jpg}
+        \subcaption{Clocked Once from Initial State}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff/clk-2.jpg}
+        \subcaption{Clocked Twice from Initial State}
+    \end{minipage}
+    \caption{D Flipflop Toggler}
+    \label{fig:a3-2-res}
+\end{figure}
+
+\subsubsection{観測された挙動}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed State Transition Table of D Flipflop Toggler}
+    \label{tab:a3-2-res-st}
+    \begin{tabular}{cccl}
+        \hline
+        $CK$ & $Q$ & $Q_{\text{next}}$ & Action \\
+        \hline
+        $\uparrow$ & 0 & 1 & Toggle \\
+        $\uparrow$ & 1 & 0 & Toggle \\
+        $\downarrow$ & * & Q & Hold \\
+        \hline
+    \end{tabular}
+\end{table}
+
+\subsection{課題 3-3}
+
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit/initial.jpg}
+        \subcaption{Initial State}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit/clk-6.jpg}
+        \subcaption{Clocked Six Times from Initial State}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit/clk-15.jpg}
+        \subcaption{Clocked Fifteen Times from Initial State}
+    \end{minipage}
+    \caption{4 Bits D Flipflop Counter (LSB on Right)}
+    \label{fig:a3-3-res}
+\end{figure}
+
+\subsubsection{観測された挙動}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed State Transition Table of 4 Bits D Flipflop Counter}
+    \label{tab:a3-3-res-st}
+    \begin{tabular}{cccccccl}
+        \hline
+        $Q$ & CK & $Q_{\text{next}}$ & $D_A$ & $D_B$ & $D_C$ & $D_D$ & Action \\
+        \hline
+        0 & $\uparrow$ & 1 & 0 & 0 & 0 & 0 & Count \\
+        1 & $\uparrow$ & 2 & 1 & 1 & 1 & 1 & Count \\
+        2 & $\uparrow$ & 3 & 0 & 1 & 1 & 1 & Count \\
+        3 & $\uparrow$ & 4 & 1 & 0 & 1 & 1 & Count \\
+        4 & $\uparrow$ & 5 & 0 & 0 & 1 & 1 & Count \\
+        5 & $\uparrow$ & 6 & 1 & 1 & 0 & 1 & Count \\
+        6 & $\uparrow$ & 7 & 0 & 1 & 0 & 1 & Count \\
+        7 & $\uparrow$ & 8 & 1 & 0 & 0 & 1 & Count \\
+        8 & $\uparrow$ & 9 & 0 & 0 & 0 & 1 & Count \\
+        9 & $\uparrow$ & 10 & 1 & 1 & 1 & 0 & Count \\
+        10 & $\uparrow$ & 11 & 0 & 1 & 1 & 0 & Count \\
+        11 & $\uparrow$ & 12 & 1 & 0 & 1 & 0 & Count \\
+        12 & $\uparrow$ & 13 & 0 & 0 & 1 & 0 & Count \\
+        13 & $\uparrow$ & 14 & 1 & 1 & 0 & 0 & Count \\
+        14 & $\uparrow$ & 15 & 0 & 1 & 0 & 0 & Count \\
+        15 & $\uparrow$ & 0 & 1 & 0 & 0 & 0 & Count \\
+        * & $\downarrow$ & $Q$ & * & * & * & * & Hold \\
+        \hline
+    \end{tabular}
+\end{table}
+
+\subsection{課題 3-4}
+
+? にはANDゲートを使用した.
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit-cond/initial.jpg}
+        \subcaption{Initial State}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit-cond/clk-3.jpg}
+        \subcaption{Clocked 3 Times from Initial State}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit-cond/halt.jpg}
+        \subcaption{Halt State}
+    \end{minipage}
+    \caption{4 Bits D Flipflop Counter with Halt Condition (LSB on Right)}
+    \label{fig:a3-4-res}
+\end{figure}
+
+\subsubsection{観測された挙動}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed State Transition Table of 4 Bits D Flipflop Counter with Halt Condition}
+    \label{tab:a3-4-res-st}
+    \begin{tabular}{cccccccl}
+        \hline
+        $Q$ & CK & $Q_{\text{next}}$ & $D_A$ & $D_B$ & $D_C$ & $D_D$ & Action \\
+        \hline
+        0 & $\uparrow$ & 1 & 0 & 0 & 0 & 0 & Count \\
+        1 & $\uparrow$ & 2 & 1 & 1 & 1 & 1 & Count \\
+        2 & $\uparrow$ & 3 & 0 & 1 & 1 & 1 & Count \\
+        3 & $\uparrow$ & 4 & 1 & 0 & 1 & 1 & Count \\
+        4 & $\uparrow$ & 5 & 0 & 0 & 1 & 1 & Count \\
+        5 & $\uparrow$ & 6 & 1 & 1 & 0 & 1 & Count \\
+        6 & $\uparrow$ & 7 & 0 & 1 & 0 & 1 & Count \\
+        7 & $\uparrow$ & 7 & 1 & 0 & 0 & 1 & Halt \\
+        * & $\downarrow$ & $Q$ & * & * & * & * & Hold \\
+        \hline
+    \end{tabular}
+\end{table}
+
+\subsection{応用課題 A}
+
+\cref{tab:a3-3-res-st}での状態0から状態1になる時の応答波形は\cref{fig:aa-res}となった.
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=7cm]{./assets/t-2/result/signal-timing/first-second-bit.jpg}
+        \subcaption{First and Second Bits}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=7cm]{./assets/t-2/result/signal-timing/third-fourth-bit.jpg}
+        \subcaption{Third and Forth Bits}
+    \end{minipage}
+    \caption{Response Signals of Counter Output when State Transitions from 0 to 1}
+    \label{fig:aa-res}
+\end{figure}
+
+各出力がTC74HC74のHレベルの入力電圧に到達するまでの時間を応答時間とし,
+それぞれの応答時間の概算は\cref{tab:aa-res}となった.
+
+\begin{table}[H]
+    \centering
+    \caption{Response Time of Each Bit}
+    \label{tab:aa-res}
+    \begin{tabular}{cr}
+        \hline
+        Bit & Response Time (ns) \\
+        \hline
+        0 & 30 \\
+        1 & 60 \\
+        2 & 80 \\
+        3 & 75 \\
+        \hline
+    \end{tabular}
+\end{table}

sections/t-2/reflection.tex

@@ -0,0 +1,347 @@
+\section{考察}
+
+\subsection{課題 1-1}
+
+この実験ではTC74HC08のANDゲートを使用した.
+
+ANDゲートは等価回路は\cref{fig:and-gate-equi}のようにスイッチが2つ直列に接続された回路で, 両方のスイッチが閉じた時のみ, Hレベルを出力する.
+
+\begin{figure}[H]
+    \centering
+    \begin{circuitikz}
+        \ctikzset{switches/scale=1}
+        \ctikzset{resistors/scale=1}
+        \ctikzset{diodes/scale=1}
+        \draw (0,0) node[vcc]{$V_{DD}$} to [normal open switch, l={$A$}] ++(2,0) to [normal open switch, l={$B$}] ++(2,0) coordinate (out) to [R] ++(2,0) node[ground]{};
+        \draw (out) to [short, *-o] ++(0,0.5) node[above]{Output};
+    \end{circuitikz}
+    \caption{AND Gate Equivalent Circuit}
+    \label{fig:and-gate-equi}
+\end{figure}
+
+このことから, \cref{tab:a1-1-res-tt}で示した結果は両方の入力がHレベルの時だけ出力がHレベルとなっているため, 理論と一致することが分かる.
+
+\subsection{課題 1-2}
+
+\Cref{tab:a1-2-res-tt}より, 全ての入力がHレベルの時のみ出力がLレベルとなっている.
+NANDゲートはANDゲートの否定なので, 結果は理屈に沿っている.
+
+\subsection{課題 1-3}
+
+\Cref{fig:a1-3-cd}より, 各ゲートの出力は\cref{equ:output-of-each-gate-a1-3}となる.
+
+\begin{equation}
+    \label{equ:output-of-each-gate-a1-3}
+    \begin{split}
+        O_1 &= A_{\text{IN}} \cdot B_{\text{IN}} \\
+        O_2 &= C_{\text{IN}} \cdot D_{\text{IN}} \\
+        D_p &= O_1 \cdot O_2 = (A_{\text{IN}} \cdot B_{\text{IN}}) \cdot (C_{\text{IN}} \cdot D_{\text{IN}})
+    \end{split}
+\end{equation}
+
+\Cref{equ:output-of-each-gate-a1-3}より, 真理値表は\cref{tab:theoretical-a1-3}となる.
+
+\begin{table}[H]
+    \centering
+    \caption{Theoretical Truth Table of $D_p = (A_{\text{IN}} \cdot B_{\text{IN}}) \cdot (C_{\text{IN}} \cdot D_{\text{IN}})$}
+    \label{tab:theoretical-a1-3}
+    \begin{tabular}{ccccc}
+        \hline
+        $A_{\text{IN}}$ & $B_{\text{IN}}$ & $C_{\text{IN}}$ & $D_{\text{IN}}$ & $D_p$ \\
+        \hline
+        0 & 0 & 0 & 0 & 0 \\
+        1 & 0 & 0 & 0 & 0 \\
+        0 & 1 & 0 & 0 & 0 \\
+        1 & 1 & 0 & 0 & 0 \\
+        0 & 0 & 1 & 0 & 0 \\
+        1 & 0 & 1 & 0 & 0 \\
+        0 & 1 & 1 & 0 & 0 \\
+        1 & 1 & 1 & 0 & 0 \\
+        0 & 0 & 0 & 1 & 0 \\
+        1 & 0 & 0 & 1 & 0 \\
+        0 & 1 & 0 & 1 & 0 \\
+        1 & 1 & 0 & 1 & 0 \\
+        0 & 0 & 1 & 1 & 0 \\
+        1 & 0 & 1 & 1 & 0 \\
+        0 & 1 & 1 & 1 & 0 \\
+        1 & 1 & 1 & 1 & 1 \\
+        \hline
+    \end{tabular}
+\end{table}
+
+\Cref{tab:theoretical-a1-3}より, 出力$D_p$が1となるのは全入力が1の時だけであり, この条件を論理式にすると\cref{equ:a1-3-final}となり, \cref{equ:output-of-each-gate-a1-3}で示した$D_p$と等価な式になる.
+
+\begin{equation}
+    \label{equ:a1-3-final}
+    d_p = A_{\text{IN}} \cdot B_{\text{IN}} \cdot C_{\text{IN}} \cdot D_{\text{IN}}
+\end{equation}
+
+\subsection{課題 1-4}
+
+\Cref{fig:a1-4-cd}の出力は\cref{equ:a1-4-out}で示され, ド・モルガンの定理で変形していくと\cref{equ:a1-4-de-morganed}となる.
+
+\begin{equation}
+    \label{equ:a1-4-out}
+    D_p = \overline{(A_{\text{IN}} \cdot B_{\text{IN}}) \cdot (C_{\text{IN}} \cdot D_{\text{IN}})}
+\end{equation}
+
+\begin{equation}
+    \label{equ:a1-4-de-morganed}
+    \begin{split}
+        D_p &= \overline{(A_{\text{IN}} \cdot B_{\text{IN}}) \cdot (C_{\text{IN}} \cdot D_{\text{IN}})} = \overline{A_{\text{IN}} \cdot B_{\text{IN}}} + \overline{C_{\text{IN}} \cdot D_{\text{IN}}} \\
+            &= \overline{A_{\text{IN}}} + \overline{B_{\text{IN}}} + \overline{C_{\text{IN}}} + \overline{D_{\text{IN}}} = \overline{A_{\text{IN}} \cdot B_{\text{IN}} \cdot C_{\text{IN}} \cdot D_{\text{IN}}}
+    \end{split}
+\end{equation}
+
+論理式の等価は真理値表の一致を意味するので, \cref{equ:a1-4-de-morganed}で示した論理式の真理値表も全て一致する.
+\Cref{tab:a1-4-res-tt}の真理値表は\cref{tab:a1-2-res-tt}のものと一致している, よってこれら2つの論理式は等価である.
+
+\subsection{課題 2-1}
+
+デコーダ回路とはある意味を持つ小さなコードを別の対応するより大きなコードへの写像を取る回路のことである.
+今回の場合は4ビットの二進数から7セグメントLEDの点灯パターンへの写像を論理回路で実装している.
+
+7セグメントLEDデコーダのTC4511はそれぞれの出力が論理式の出力となってる.
+
+\subsection{課題 2-2B}
+
+この回路を制作するにあたって, まずは\cref{tab:a2-2b-tt-design}の真理値表を考える.
+
+\begin{table}[H]
+    \centering
+    \caption{Truth Table for Designing 7 Segment Hexadecimal Decoder}
+    \label{tab:a2-2b-tt-design}
+    \begin{tabular}{ccccccccccc}
+        \hline
+        a & b & c & d & A & B & C & D & E & F & G \\
+        \hline
+        0 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 1 & 1 \\
+        1 & 1 & 0 & 1 & 0 & 0 & 1 & 1 & 1 & 1 & 1 \\
+        0 & 0 & 1 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 \\
+        1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 1 \\
+        0 & 1 & 1 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 1 \\
+        1 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 \\
+        \hline
+    \end{tabular}
+\end{table}
+
+ここで, dの値が全てHレベルであるので, 一旦省略する.
+この真理値表にもとずいたそれぞれのセグメントの論理式は\cref{equ:a2-2b-equ-design}となる.
+
+\begin{equation}
+    \label{equ:a2-2b-equ-design}
+    \begin{split}
+        A &= \overline{(a \cdot b \cdot \bar{c}) + (a \cdot \bar{b} \cdot c)} \\
+        B &= (\bar{a} \cdot b \cdot \bar{c}) + (a \cdot \bar{b} \cdot c) \\
+        C &= B + (a \cdot b \cdot \bar{c}) \\
+        D &= \overline{(\bar{a} \cdot b \cdot \bar{c}) + (a \cdot b \cdot c)} \\
+        E &= d \\
+        F &= \overline{a \cdot \bar{b} \cdot c} \\
+        G &= \overline{\bar{a} \cdot \bar{b} \cdot c}
+    \end{split}
+\end{equation}
+
+Eセグメントには省略していたdの値を1との論理積として戻した.
+これら論理式にカルノー図を適応したが, もとが十分簡略化されていたためか, あまり有用ではなかった.
+かわりに, 複数式に共通する項を1つのユニットとして共有して使用することにした.
+
+共通項は\cref{equ:a2-2b-common}とした.
+
+\begin{equation}
+    \label{equ:a2-2b-common}
+    \begin{split}
+        X &= (a \cdot b \cdot \bar{c}) \\
+        Y &= (a \cdot \bar{b} \cdot c) \\
+        Z &= (\bar{a} \cdot b \cdot \bar{c})
+    \end{split}
+\end{equation}
+
+また, 禁止条件が入力された際の真理値値表は\cref{tab:a2-2b-not-allowed}となった.
+
+\begin{table}[H]
+    \centering
+    \caption{Truth Table for Disallowed Conditions}
+    \label{tab:a2-2b-not-allowed}
+    \begin{tabular}{ccccc}
+        \hline
+        a & b & c & d & $\overline{\text{EN}}$ \\
+        \hline
+        * & * & * & 0 & 1 \\
+        * & 0 & 0 & 1 & 1 \\
+        \hline
+    \end{tabular}
+\end{table}
+
+上記の真理値表から論理式を作成すると\cref{equ:a2-2b-not-allowed-equ}となった.
+
+\begin{equation}
+    \label{equ:a2-2b-not-allowed-equ}    
+    \text{EN} = d \cdot (b + c)
+\end{equation}
+
+この論理式の出力でNch MOSFETを駆動させ, 7セグメントLEDのコモンカソードを制御することで一括で消灯させることにした.
+
+これら論理式から回路を制作すると\cref{fig:a2-2b-cd}となった.
+
+\begin{figure}[tbh]
+    \centering
+    \begin{circuitikz}[scale=0.7]
+        \ctikzset{logic ports=ieee}
+        \ctikzset{logic ports/scale=0.7}
+        \ctikzset{resistors/scale=0.7}
+
+        \node [and port, number inputs=3] at (-5,4) (X) {};
+        \node [and port, number inputs=3] at (-5,2) (Y) {};
+        \node [and port, number inputs=3] at (-5,0) (Z) {};
+        \node [nor port] at (0,4) (A) {};
+        \node [or port] at (0,2) (B) {};
+        \node [or port] at (0,0) (C) {};
+        \node [and port, number inputs=3] at (5,4) (m) {};
+        \node [nor port, anchor=in 2] at ($(m.out) + (1,0)$) (D) {};
+        \node [not port] at (5,2) (F) {};
+        \node [nand port, number inputs=3] at (5,0) (G) {};
+
+        \node [notcirc,left] at (X.bin 3) {};
+        \node [notcirc,left] at (Y.bin 2) {};
+        \node [notcirc,left] at (Z.bin 1) {};
+        \node [notcirc,left] at (Z.bin 3) {};
+        \node [notcirc,left] at (G.bin 1) {};
+        \node [notcirc,left] at (G.bin 2) {};
+
+        \draw (X.in 1) ++(-0.5,0) node[left]{a} to [short, o-] (X.in 1);
+        \draw (X.in 2) ++(-0.5,0) node[left]{b} to [short, o-] (X.in 2);
+        \draw (X.in 3) ++(-0.5,0) node[left]{c} to [short, o-] (X.in 3);
+        \draw (X.out) to [short, -o] ++(0.5,0) node[right]{X};
+        \draw (Y.in 1) ++(-0.5,0) node[left]{a} to [short, o-] (Y.in 1);
+        \draw (Y.in 2) ++(-0.5,0) node[left]{b} to [short, o-] (Y.in 2);
+        \draw (Y.in 3) ++(-0.5,0) node[left]{c} to [short, o-] (Y.in 3);
+        \draw (Y.out) to [short, -o] ++(0.5,0) node[right]{Y};
+        \draw (Z.in 1) ++(-0.5,0) node[left]{a} to [short, o-] (Z.in 1);
+        \draw (Z.in 2) ++(-0.5,0) node[left]{b} to [short, o-] (Z.in 2);
+        \draw (Z.in 3) ++(-0.5,0) node[left]{c} to [short, o-] (Z.in 3);
+        \draw (Z.out) to [short, -o] ++(0.5,0) node[right]{Z};
+
+        \draw (A.in 1) ++(-0.5,0) node[left]{X} to [short, o-] ++(0.5,0);
+        \draw (A.in 2) ++(-0.5,0) node[left]{Y} to [short, o-] ++(0.5,0);
+        \draw (A.out) to [short, -o] ++(0.5,0) node[right]{A};
+        \draw (B.in 1) ++(-0.5,0) node[left]{Y} to [short, o-] ++(0.5,0);
+        \draw (B.in 2) ++(-0.5,0) node[left]{Z} to [short, o-] ++(0.5,0);
+        \draw (B.out) to [short, -o] ++(0.5,0) node[right]{B};
+        \draw (C.in 1) ++(-0.5,0) node[left]{B} to [short, o-] ++(0.5,0);
+        \draw (C.in 2) ++(-0.5,0) node[left]{X} to [short, o-] ++(0.5,0);
+        \draw (C.out) to [short, -o] ++(0.5,0) node[right]{C};
+        \draw (m.in 1) ++(-0.5,0) node[left]{a} to [short, o-] ++(0.5,0);
+        \draw (m.in 2) ++(-0.5,0) node[left]{b} to [short, o-] ++(0.5,0);
+        \draw (m.in 3) ++(-0.5,0) node[left]{c} to [short, o-] ++(0.5,0);
+        \draw (m.out) -- (D.in 2);
+        \draw (D.in 1) ++(-0.5,0) node[left]{Z} to [short, o-] ++(0.5,0);
+        \draw (D.out) to [short, -o] ++(0.5,0) node[right]{D};
+        \draw (F.in) ++(-0.5,0) node[left]{Y} to [short, o-] ++(0.5,0);
+        \draw (F.out) to [short, -o] ++(0.5,0) node[right]{F};
+        \draw (G.in 1) ++(-0.5,0) node[left]{a} to [short, o-] (G.in 1);
+        \draw (G.in 2) ++(-0.5,0) node[left]{b} to [short, o-] (G.in 2);
+        \draw (G.in 3) ++(-0.5,0) node[left]{c} to [short, o-] (G.in 3);
+        \draw (G.out) to [short, -o] ++(0.5,0) node[right]{G};
+
+        \draw (-1.5, -2) node[left]{d} to [short, o-o] ++(3,0) node[right]{E};
+
+        \draw (G.out) ++(1,-2) node[above]{Common Cathode} to [short, o-] ++(0,-1) node[nigfete,anchor=D](Q){} (Q.S) -- ++(0,-1.3) node[ground]{} (Q.G) to [short, -*] ++(-1,0) coordinate (Qin) to [R, l={$330 \ \Omega$}] ++(0,-2) node[ground]{};
+        \draw (Qin) -- ++(-1,0) node[and port, anchor=out](ENAnd){};
+        \draw (ENAnd.in 1) to [short, -o] ++(-0.5,0) node[left]{d};
+        \draw (ENAnd.in 2) -- ++(-1,0) node[or port, anchor=out](ENOr){};
+        \draw (ENOr.in 1) to [short, -o] ++(-0.5,0) node[left]{b};
+        \draw (ENOr.in 2) to [short, -o] ++(-0.5,0) node[left]{c};
+
+        \ctikzset{resistors/scale=0.5}
+        \draw (-7,-4) node[dipchip, num pins=14, no topmark, external pins width=0.0, hide numbers](LED){} (LED) node[bare7seg]{};
+        \node [left, font=\tiny] at (LED.bpin 14) {A};
+        \node [left, font=\tiny] at (LED.bpin 13) {B};
+        \node [left, font=\tiny] at (LED.bpin 12) {C};
+        \node [left, font=\tiny] at (LED.bpin 11) {D};
+        \node [left, font=\tiny] at (LED.bpin 10) {E};
+        \node [left, font=\tiny] at (LED.bpin 9) {F};
+        \node [left, font=\tiny] at (LED.bpin 8) {G};
+        \node [above, font=\tiny] at (LED.s) {Cathode};
+        \draw (LED.bpin 14) to[R] ++(1.5,0) to [short,-o] ++(0.5,0) node[right]{A};
+        \draw (LED.bpin 13) to[R] ++(1.5,0) to [short,-o] ++(0.5,0) node[right]{B};
+        \draw (LED.bpin 12) to[R] ++(1.5,0) to [short,-o] ++(0.5,0) node[right]{C};
+        \draw (LED.bpin 11) to[R] ++(1.5,0) to [short,-o] ++(0.5,0) node[right]{D};
+        \draw (LED.bpin 10) to[R] ++(1.5,0) to [short,-o] ++(0.5,0) node[right]{E};
+        \draw (LED.bpin 9) to[R] ++(1.5,0) to [short,-o] ++(0.5,0) node[right]{F};
+        \draw (LED.bpin 8) to[R] ++(1.5,0) to [short,-o] ++(0.5,0) node[right]{G};
+        \draw (LED.s) to [short,-o] ++(0,-1) node[right]{Common Cathode};
+
+        \draw[dash pattern=on 4pt off 4pt, thick] (LED.ne) ++(0.1, 0.1) rectangle ($(LED.se) + (1.4,-0.1)$);
+        \draw (LED.se) ++(0.7,-0.1) node[below]{$330 \ \Omega$};
+    \end{circuitikz}
+    \caption{Circuit Diagram of 7 Segment Hexadecimal Decoder}
+    \label{fig:a2-2b-cd}
+\end{figure}
+
+\subsection{課題 3-1}
+
+今回の実験では\cref{fig:a3-1-stg}の状態遷移を行うNOR構成のRSフリップフロップを作成した.
+
+\begin{figure}[tbh]
+    \centering
+    \begin{tikzpicture}[shorten >=1pt, node distance=2cm, auto]
+        \node [state] (Q0) {$Q_0$};
+        \node [state] (Q1) [right of=Q0] {$Q_1$};
+
+        \path[->] (Q0) edge [bend left] node[above] {$01/1$} (Q1);
+        \path[->] (Q1) edge [bend left] node[below] {$10/0$} (Q0);
+        \path[->] (Q0) edge [loop left] node[left] {$00/0$} () (Q1) edge [loop right] node[right] {$00/1$} ();
+    \end{tikzpicture}
+    \caption{
+        \parbox[t]{8cm}{State Transition Graph of RS Flipflop, the Edge Labels Show Input R, Input S, and Output Q from Left}
+    }
+    \label{fig:a3-1-stg}
+\end{figure}
+
+この構成ではRとS共に1が入力された時が禁止状態となる.
+禁止状態では, 両方のNORゲートに1つ以上のHレベルの入力がかかり, 双方出力が0となりフリップフロップとしての機能を喪失する.
+どちらかの入力がLレベルになるまでこの機能は回復しない.
+
+\subsection{課題 3-3}
+
+今回の実験で作成したカウンタは二進数のビットごとの否定を出力するものとなった.
+これは初期状態では全ての出力$Q$がLレベルで, 次の状態で入力Dに印加されるのは全て否定出力$\bar{Q}$のHレベルとなるためである.
+
+この回路は複数のDフリップフロップの出力が次のフリップフロップのクロック入力へ数珠接続した非同期のカウンタとなる.
+
+\subsection{課題 3-4}
+
+最下位のDフリップフロップのクロックをパルスさせるには?の論理ゲートの出力をNANDゲートの入力関係無しにボタンからのオン・オフでトグルさせる必要がある.
+手元にあるゲートの中でこのクロックをパルスさせることが出来たのはANDゲートであったが, NANDゲートの出力がLレベルになるカウンタ出力の組み合わせで状態の遷移が停止してしまった.
+
+これはANDゲートの出力をHレベルにするには2つの入力がHレベルである必要があるが, NANDゲートの出力がLレベルになってしまった以上, ボタンの出力のみでANDゲートの出力を変えることが出来なくなってしまったことに起因する.
+
+このカウンタを一巡させるには1つのHレベル入力のみで出力をパルスさせ, かつ両方がHレベルのときには出力をLレベルにすることが出来る論理ゲートが必要である.
+その論理ゲートこそXOR(排他的論理和)である. この論理ゲートの真理値表は\cref{tab:xor-gate-tt}で, 一方の入力がHレベルである時だけ出力をHレベルにすることが出来る\supercite{digital-circuit:xor}.
+
+\begin{table}[H]
+    \centering
+    \caption{Truth Table of XOR Gate}
+    \label{tab:xor-gate-tt}
+    \begin{tabular}{ccc}
+        \hline
+        a & b & x \\
+        \hline
+        0 & 0 & 0 \\
+        1 & 0 & 1 \\
+        0 & 1 & 1 \\
+        1 & 1 & 0 \\
+        \hline
+    \end{tabular}
+\end{table}
+
+\subsection{応用課題 A}
+
+\Cref{fig:aa-res}と\cref{tab:aa-res}より, 信号は最下位ビットから順番に立ち上がっている様子が分かる.
+しかし, $2^2$のビットは$2^3$のビットに遅れてTC74HC74のHレベルの入力電圧である3.15 Vに到達した.
+これにはIC内部や, 入力端子の寄生容量が関係していると思われる\supercite{tc74hc74}. 
+
+これら遅延は非同期カウンタの性質上避けられない性質で, クロックとほぼ同時に状態が遷移する同期式のカウンタならこの遅延を少なくすることができる.
+
+このことから, この回路で入力できる最大周波数の理論値は$\frac{1}{80 \ \text{ns}} = 12.5 \ \text{MHz}$となる.
+実際, ファンクションジェネレータで16 MHz付近の周波数をクロックに入力すると動作が不安定になった.

sections/t-2/theory.tex

@@ -0,0 +1,191 @@
+\section{理論}
+
+\subsection{ディジタル}
+
+ディジタルとは最小単位が存在する物理量であり, 連続的で最小単位が存在しないアナログと対になる.
+この最小単位というのは時間や電圧などの刻み幅を決めるもので分解能ともいう. 分解能を高くすれば, 真の値と観測値の誤差が小さくなる.
+ディジタルには「誰が測っても同じになる」ことと「多少ノイズが混じっても大丈夫」という長所があり, 逆に「最小単位より小さいものは測れない」という短所がある.
+ディジタルにより, 現実世界の様々な現象をある一定の精度で数値的に解析・再現することが出来るようになった\supercite{digital-circuit:digital}.
+
+\begin{figure}[tbh]
+    \centering
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=0.9\textwidth]{./assets/t-2/analog-example.png}
+        \subcaption{Analog}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=0.9\textwidth]{./assets/t-2/digitize-example.png}
+        \subcaption{Digital}
+    \end{minipage}
+    \caption{Example of Analog and Digital Signal}
+\end{figure}
+
+\subsection{二進数}
+
+二進数とは0と1などの二種類の記号を用いた数の表記法である.
+これにより電気のオン・オフなど回路で扱いやすい形で様々な数を表すことが出来るようになった\supercite{digital-circuit:basic-logic}.
+
+\subsection{ブール代数}
+
+ブール代数とは二値化された数に対し, 演算子や法則を定義した数学の分野である.
+ブール代数では基本的な演算子は論理和, 論理積, 論理否定である\supercite{digital-circuit:basic-logic}.
+これらの演算子の演算結果は\cref{tab:truth-table-basic}のような真理値表でまとめることが出来る\supercite{digital-circuit:truth-table}.
+
+\begin{table}[!ht]
+    \caption{Truth Tables of Basic Logic Operations}
+    \label{tab:truth-table-basic}
+    \begin{minipage}[h]{0.33\textwidth}
+        \centering
+        \subcaption{Logical And ($x = a \cdot b$)}
+        \begin{tabular}{ccc}
+            \hline
+            a & b & x \\ \hline
+            0 & 0 & 0 \\
+            1 & 0 & 0 \\
+            0 & 1 & 0 \\
+            1 & 1 & 1 \\
+            \hline
+        \end{tabular}
+    \end{minipage}
+    \begin{minipage}[h]{0.33\textwidth}
+        \centering
+        \subcaption{Logical Or ($x = a + b$)}
+        \begin{tabular}{ccc}
+            \hline
+            a & b & x \\ \hline
+            0 & 0 & 0 \\
+            1 & 0 & 1 \\
+            0 & 1 & 1 \\
+            1 & 1 & 1 \\
+            \hline
+        \end{tabular}
+    \end{minipage}
+    \begin{minipage}[h]{0.33\textwidth}
+        \centering
+        \subcaption{Logical Not ($x = \bar{a}$)}
+        \begin{tabular}{cc}
+            \hline
+            a & $\bar{\text{a}}$ \\ \hline
+            0 & 1 \\
+            1 & 0 \\
+            \hline
+        \end{tabular}
+    \end{minipage}
+\end{table}
+
+これら演算子に対する法則を\cref{equ:laws-of-boolean}に示す.
+
+\begin{equation}
+    \label{equ:laws-of-boolean}
+    \begin{aligned}
+        a + a &= a &\ \text{(Idempotent Law)} \\
+        a \cdot a &= a &\ \text{(Idempotent Law)} \\
+        a + 1 &= 1 &\ \text{(Identity Law)} \\
+        a \cdot 0 &= 0 &\ \text{(Identity Law)} \\
+        a + (a \cdot b) &= a &\ \text{(Absorption Law)} \\
+        a \cdot (a + b) &= a &\ \text{(Absorption Law)} \\
+        (a + b) + c &= a + (b + c) &\ \text{(Associative Law)} \\
+        (a \cdot b) \cdot c &= a \cdot (b \cdot c) &\ \text{(Associative Law)} \\
+        \bar{\bar{a}} &= a &\ \text{(Double Negation)}
+    \end{aligned}
+\end{equation}
+
+ブール代数の代表的な定理としてド・モルガンの定理がある.
+
+この定理は「あるブール式の各変数を否定し, 式の中の論理積と論理和を入れ替えた式は, 全体を否定した式と同じ値をとる」というもので\cref{equ:deMorgan}のような式で表現される\supercite{digital-circuit:basic-logic}.
+
+\begin{equation}\label{equ:deMorgan}
+    \overline{f(x_1, x_2, \dotsc, +, \cdot)} = f(\overline{x_1}, \overline{x_2}, \dotsc, \cdot{}, +)
+\end{equation}
+
+\subsection{論理ゲート}
+
+論理ゲートは論理演算を電気回路で表現したもので, 回路記号は\cref{fig:logic-gate-symbols}で表される\supercite{digital-circuit:gate-ic}.
+
+\begin{figure}[tbh]
+    \centering
+    \begin{circuitikz}
+        \ctikzset{logic ports=ieee}
+        \node [and port] at (0,2) {};
+        \node [nand port] at (0,0) {};
+        \node [or port] at (3,2) {};
+        \node [nor port] at (3,0) {};
+        \node [not port] at (6,1) {};
+        \node at (0,1) {AND Gate};
+        \node at (0,-1) {NAND Gate};
+        \node at (3,1) {OR Gate};
+        \node at (3,-1) {NOR Gate};
+        \node at (6,0) {NOT Gate};
+    \end{circuitikz}
+    \caption{Symbols of Logic Gates}
+    \label{fig:logic-gate-symbols}
+\end{figure}
+
+図中のNANDゲートやNORゲートはそれぞれANDゲートとORゲートの結果の論理否定を出力する.
+
+これら論理ゲートを複数個まとめてパッケージしたICが論理ゲートICと呼ばれている.
+
+\subsection{組み合わせ回路}
+
+複雑な条件を扱う論理回路は論理ゲート1つだけでは実現できない. 論理ゲートを複数種類・複数個組み合わせて作られた回路を組み合わせ回路という.
+
+組み合わせ回路を作成するにあたり, 論理式の簡略化はコストや実装空間の制限上必須である. 
+この簡略化で用いられる方法の1つがカルノー図である.
+
+カルノー図は論理式の結果を特定の条件に対応する行と列に写したもので, $x = (\bar{a} \cdot b \cdot c) + (a \cdot b \cdot \bar{c}) + (a \cdot \bar{b} \cdot \bar{c})$のカルノー図は\cref{fig:karnaugh-map-example}となる.
+
+\begin{figure}[tbh]
+    \centering
+    \begin{tabular}{|c|c|c|}
+        \hline
+        & $\bar{c}$ & $c$ \\ \hline
+        $\bar{a} \ \bar{b}$ & & \\ \hline
+        $\bar{a} \ b$ & & 1 \\ \hline
+        $a \ b$ & 1 & \\ \hline
+        $a \ \bar{b}$ & 1 & \\
+        \hline
+    \end{tabular}
+    \caption{Karnaugh Map of $x = (\bar{a} \cdot b \cdot c) + (a \cdot b \cdot \bar{c}) + (a \cdot \bar{b} \cdot \bar{c})$}
+    \label{fig:karnaugh-map-example}
+\end{figure}
+
+カルノー図から隣接する1のセルを「くくる」と論理式を簡略化することが出来る\supercite{digital-circuit:karnaugh-map}.
+今回の例では$a \cdot b \cdot \bar{c}$のセルと$a \cdot \bar{b} \cdot \bar{c}$のセルでは$b$の値によらず1になっているので, くくって $x = (a \cdot \bar{c}) + (\bar{a} \cdot b \cdot c)$を得る.
+
+\subsection{順序回路}
+
+論理回路には現在の状態と入力によって次の状態へ変化する回路が存在する. これらの回路は順序回路と呼ばれている.
+例えば, ある状態Aで入力が0の時, 出力を1にし状態Bへ, 入力が1の時, 出力を0にし状態Cへ遷移するというような回路のことである\supercite{digital-circuit:sequential-logic}.
+
+順序回路の動作を説明するには状態遷移図や状態遷移表が有効である. 
+状態遷移図は各状態をノード, 入力/出力の順で表記された状態の遷移をエッジとする有向グラフとして表現される.
+状態遷移表は入力と現状態が次にどの状態と出力をするのかを表にまとめたものである\supercite{digital-circuit:state-transition}.
+前述の例を状態遷移図と状態遷移表で表現するとそれぞれ\cref{fig:state-transition-graph-example}と\cref{tab:state-tarnsition-table-example}となる.
+
+\begin{table}[!ht]
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \begin{tikzpicture}[shorten >=1pt, node distance=2cm, auto]
+            \node [state] (A) {$A$};
+            \node [state] (B) [above right of=A] {$B$};
+            \node [state] (C) [below right of=A] {$C$};
+            \path[->] (A) edge node {$0/1$} (B) edge node {$1/0$} (C);
+        \end{tikzpicture}
+        \captionof{figure}{Example of State Transition Graph}
+        \label{fig:state-transition-graph-example}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \captionof{table}{Example of State Transition Table}
+        \label{tab:state-tarnsition-table-example}
+        \begin{tabular}{cccc}
+            \hline
+            State & Input & Next State & Output \\ \hline
+            A & 0 & B & 1 \\
+            A & 1 & C & 0 \\
+            \hline
+        \end{tabular}
+    \end{minipage}
+\end{table}

tex/depD-format.sty

@@ -14,6 +14,8 @@
 \Crefname{figure}{Fig.}{Fig.}
 \crefname{table}{Table}{Tables}
 \Crefname{table}{Table}{Tables}
+\crefname{section}{section}{sections}
+\Crefname{section}{Section}{Sections}
 \crefname{equation}{Eq.}{Eq.}
 \Crefname{equation}{Eq.}{Eq.}
 \creflabelformat{equation}{(#1)}