\section{実験結果} \subsection{課題 1-1} \subsubsection{動作} \begin{figure}[H] \centering \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/and-gate/state-00.jpg} \subcaption{$a = 0, \ b = 0$} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/and-gate/state-01.jpg} \subcaption{$a = 1, \ b = 0$} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/and-gate/state-11.jpg} \subcaption{$a = 1, \ b = 1$} \end{minipage} \caption{74HC08 AND Gate, Input A on Second from Right ($x = a \cdot b$)} \label{fig:a1-1-res} \end{figure} \subsubsection{観測された真理値表} \begin{table}[H] \centering \caption{Observed Truth Table of $x = a \cdot b$} \label{tab:a1-1-res-tt} \begin{tabular}{ccc} \hline a & b & $x$ \\ \hline 0 & 0 & 0 \\ 1 & 0 & 0 \\ 0 & 1 & 0 \\ 1 & 1 & 1 \\ \hline \end{tabular} \end{table} \subsection{課題 1-2} \subsubsection{動作} \begin{figure}[H] \centering \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/nand-4/state-0000.jpg} \subcaption{$a = 0, \ b = 0, \ c = 0, \ d = 0$} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/nand-4/state-0011.jpg} \subcaption{$a = 1, \ b = 1, \ c = 0, \ d = 0$} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/nand-4/state-1111.jpg} \subcaption{$a = 1, \ b = 1, \ c = 1, \ d = 1$} \end{minipage} \caption{HD14012BP 4 Inputs NAND Gate ($x = \overline{a \cdot b \cdot c \cdot d}$)} \label{fig:a1-2-res} \end{figure} \subsubsection{観測された真理値表} \begin{table}[H] \centering \caption{Observed Truth Table of $x = \overline{a \cdot b \cdot c \cdot d}$} \label{tab:a1-2-res-tt} \begin{tabular}{ccccc} \hline a & b & c & d & x \\ \hline 0 & 0 & 0 & 0 & 1 \\ 1 & 0 & 0 & 0 & 1 \\ 0 & 1 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 & 1 \\ 0 & 0 & 1 & 0 & 1 \\ 1 & 0 & 1 & 0 & 1 \\ 0 & 1 & 1 & 0 & 1 \\ 1 & 1 & 1 & 0 & 1 \\ 0 & 0 & 0 & 1 & 1 \\ 1 & 0 & 0 & 1 & 1 \\ 0 & 1 & 0 & 1 & 1 \\ 1 & 1 & 0 & 1 & 1 \\ 0 & 0 & 1 & 1 & 1 \\ 1 & 0 & 1 & 1 & 1 \\ 0 & 1 & 1 & 1 & 1 \\ 1 & 1 & 1 & 1 & 0 \\ \hline \end{tabular} \end{table} \subsection{課題 1-3} \subsubsection{動作} \begin{figure}[H] \centering \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/and-4/state-0000.jpg} \subcaption{$a = 0, \ b = 0, \ c = 0, \ d = 0$} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/and-4/state-0010.jpg} \subcaption{$a = 0, \ b = 1, \ c = 0, \ d = 0$} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/and-4/state-1111.jpg} \subcaption{$a = 1, \ b = 1, \ c = 1, \ d = 1$} \end{minipage} \caption{ \parbox[t]{7.5cm}{4 Inputs AND Gate with Three 2 Inputs AND Gates, \\ Input A on Most Left ($x = (a \cdot b) \cdot (c \cdot d)$)} } \label{fig:a1-3-res} \end{figure} \subsubsection{観測された真理値表} \begin{table}[H] \centering \caption{Observed Truth Table of $x = (a \cdot b) \cdot (c \cdot d)$} \label{tab:a1-3-res-tt} \begin{tabular}{ccccc} \hline a & b & c & d & x \\ \hline 0 & 0 & 0 & 0 & 0 \\ 1 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 & 0 \\ 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 0 \\ 1 & 0 & 1 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 \\ 1 & 1 & 1 & 0 & 0 \\ 0 & 0 & 0 & 1 & 0 \\ 1 & 0 & 0 & 1 & 0 \\ 0 & 1 & 0 & 1 & 0 \\ 1 & 1 & 0 & 1 & 0 \\ 0 & 0 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 & 0 \\ 0 & 1 & 1 & 1 & 0 \\ 1 & 1 & 1 & 1 & 1 \\ \hline \end{tabular} \end{table} \subsection{課題 1-4} \subsubsection{動作} \begin{figure}[H] \centering \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/nand-from-ands/state-0000.jpg} \subcaption{$a = 0, \ b = 0, \ c = 0, \ d = 0$} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/nand-from-ands/state-0101.jpg} \subcaption{$a = 1, \ b = 0, \ c = 1, \ d = 0$} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/nand-from-ands/state-1111.jpg} \subcaption{$a = 1, \ b = 1, \ c = 1, \ d = 1$} \end{minipage} \caption{ \parbox[t]{8cm}{4 Inputs NAND Gate with Three 2 Inputs AND Gates and \\ a NOT Gate, Input A on Most Left ($x = \overline{(a \cdot b) \cdot (c \cdot d)}$)} } \label{fig:a1-4-res} \end{figure} \subsubsection{観測された真理値表} \begin{table}[H] \centering \caption{Observed Truth Table of $x = \overline{(a \cdot b) \cdot (c \cdot d)}$} \label{tab:a1-4-res-tt} \begin{tabular}{ccccc} \hline a & b & c & d & x \\ \hline 0 & 0 & 0 & 0 & 1 \\ 1 & 0 & 0 & 0 & 1 \\ 0 & 1 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 & 1 \\ 0 & 0 & 1 & 0 & 1 \\ 1 & 0 & 1 & 0 & 1 \\ 0 & 1 & 1 & 0 & 1 \\ 1 & 1 & 1 & 0 & 1 \\ 0 & 0 & 0 & 1 & 1 \\ 1 & 0 & 0 & 1 & 1 \\ 0 & 1 & 0 & 1 & 1 \\ 1 & 1 & 0 & 1 & 1 \\ 0 & 0 & 1 & 1 & 1 \\ 1 & 0 & 1 & 1 & 1 \\ 0 & 1 & 1 & 1 & 1 \\ 1 & 1 & 1 & 1 & 0 \\ \hline \end{tabular} \end{table} \subsection{課題 2-1} \subsubsection{動作} \begin{figure}[H] \centering \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/7seg-bcd/state-0.jpg} \subcaption{$a = 0, \ b = 0, \ c = 0, \ d = 0$} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/7seg-bcd/state-7.jpg} \subcaption{$a = 1, \ b = 1, \ c = 1, \ d = 0$} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/7seg-bcd/invalid.jpg} \subcaption{$a = 0, \ b = 1, \ c = 0, \ d = 1$} \end{minipage} \caption{7 Segment Driver (4 Bits BDC Input, LSB on Left)} \label{fig:a2-1-res} \end{figure} \subsubsection{観測された真理値表} \begin{table}[H] \centering \caption{Observed Truth Table of 7 Segment Driver} \label{tab:a2-1-res-tt} \begin{tabular}{ccccccccccc} \hline a & b & c & d & A & B & C & D & E & F & G \\ \hline 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 0 \\ 1 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & 1 & 0 & 1 & 1 & 0 & 1 \\ 1 & 1 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 1 \\ 0 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 1 & 1 \\ 1 & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 \\ 0 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 1 \\ 1 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\ 1 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 1 & 1 \\ 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ \hline \end{tabular} \end{table} \subsection{課題 2-2B} \subsubsection{動作} \begin{figure}[H] \centering \begin{minipage}[h]{0.45\textwidth} \centering \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-a.jpg} \subcaption{$a = 0, \ b = 1, \ c = 0, \ d = 1$} \end{minipage} \begin{minipage}[h]{0.45\textwidth} \centering \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-b.jpg} \subcaption{$a = 1, \ b = 1, \ c = 0, \ d = 1$} \end{minipage} \begin{minipage}[h]{0.45\textwidth} \centering \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-c.jpg} \subcaption{$a = 0, \ b = 0, \ c = 1, \ d = 1$} \end{minipage} \begin{minipage}[h]{0.45\textwidth} \centering \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-d.jpg} \subcaption{$a = 1, \ b = 0, \ c = 1, \ d = 1$} \end{minipage} \begin{minipage}[h]{0.45\textwidth} \centering \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-e.jpg} \subcaption{$a = 0, \ b = 1, \ c = 1, \ d = 1$} \end{minipage} \begin{minipage}[h]{0.45\textwidth} \centering \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-f.jpg} \subcaption{$a = 1, \ b = 1, \ c = 1, \ d = 1$} \end{minipage} \begin{minipage}[h]{0.45\textwidth} \centering \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/invalid.jpg} \subcaption{$a = 1, \ b = 0, \ c = 0, \ d = 1$} \end{minipage} \hspace{0.45\textwidth} \caption{7 Segment Hexadecimal Decoder 10-15 Only (4 Bits BCD Input, LSB on Left)} \label{fig:a2-2b-res} \end{figure} \subsubsection{観測された真理値表} \begin{table}[H] \centering \caption{Observed Truth Table of 7 Segment Hexadecimal Decoder (* Indicates Don't Care Term)} \label{tab:a2-2b-res-tt} \begin{tabular}{ccccccccccc} \hline a & b & c & d & A & B & C & D & E & F & G \\ \hline * & * & * & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ * & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 1 & 1 \\ 1 & 1 & 0 & 1 & 0 & 0 & 1 & 1 & 1 & 1 & 1 \\ 0 & 0 & 1 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 1 \\ 0 & 1 & 1 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 1 \\ 1 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 \\ \hline \end{tabular} \end{table} \subsection{課題 3-1} \subsubsection{動作} \begin{figure}[H] \centering \begin{minipage}[h]{0.45\textwidth} \centering \includegraphics[width=5cm]{./assets/t-2/result/rs-ff/initial.jpg} \subcaption{Initial State} \end{minipage} \begin{minipage}[h]{0.45\textwidth} \centering \includegraphics[width=5cm]{./assets/t-2/result/rs-ff/s-hold.jpg} \subcaption{Set Hold} \end{minipage} \begin{minipage}[h]{0.45\textwidth} \centering \includegraphics[width=5cm]{./assets/t-2/result/rs-ff/s-release.jpg} \subcaption{Set Release} \end{minipage} \begin{minipage}[h]{0.45\textwidth} \centering \includegraphics[width=5cm]{./assets/t-2/result/rs-ff/r-hold.jpg} \subcaption{Reset Hold} \end{minipage} \caption{ \parbox[t]{8cm}{RS Latch with OR Gates and NOT Gates (LEDs Represent Set, Reset, Inverted Output, Output from Left)} } \label{fig:a3-1-res} \end{figure} \subsubsection{観測された挙動} \begin{table}[H] \centering \caption{Observed State Transition Table of RS Latch} \label{tab:a3-1-res-st} \begin{tabular}{ccccl} \hline $R$ & $S$ & $Q$ & $\overline{Q}$ & Action \\ \hline 0 & 0 & $Q$ & $\overline{Q}$ & Hold \\ 0 & 1 & 1 & 0 & Set \\ 1 & 0 & 0 & 1 & Reset \\ 1 & 1 & X & X & Unstable Behaviour \\ \hline \end{tabular} \end{table} \subsection{課題 3-2} \subsubsection{動作} \begin{figure}[H] \centering \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/d-ff/initial.jpg} \subcaption{Initial State} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/d-ff/clk-1.jpg} \subcaption{Clocked Once from Initial State} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/d-ff/clk-2.jpg} \subcaption{Clocked Twice from Initial State} \end{minipage} \caption{D Flipflop Toggler} \label{fig:a3-2-res} \end{figure} \subsubsection{観測された挙動} \begin{table}[H] \centering \caption{Observed State Transition Table of D Flipflop Toggler} \label{tab:a3-2-res-st} \begin{tabular}{cccl} \hline $CK$ & $Q$ & $Q_{\text{next}}$ & Action \\ \hline $\uparrow$ & 0 & 1 & Toggle \\ $\uparrow$ & 1 & 0 & Toggle \\ $\downarrow$ & * & Q & Hold \\ \hline \end{tabular} \end{table} \subsection{課題 3-3} \subsubsection{動作} \begin{figure}[H] \centering \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit/initial.jpg} \subcaption{Initial State} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit/clk-6.jpg} \subcaption{Clocked Six Times from Initial State} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit/clk-15.jpg} \subcaption{Clocked Fifteen Times from Initial State} \end{minipage} \caption{4 Bits D Flipflop Counter (LSB on Right)} \label{fig:a3-3-res} \end{figure} \subsubsection{観測された挙動} \begin{table}[H] \centering \caption{Observed State Transition Table of 4 Bits D Flipflop Counter} \label{tab:a3-3-res-st} \begin{tabular}{cccccccl} \hline $Q$ & CK & $Q_{\text{next}}$ & $D_A$ & $D_B$ & $D_C$ & $D_D$ & Action \\ \hline 0 & $\uparrow$ & 1 & 0 & 0 & 0 & 0 & Count \\ 1 & $\uparrow$ & 2 & 1 & 1 & 1 & 1 & Count \\ 2 & $\uparrow$ & 3 & 0 & 1 & 1 & 1 & Count \\ 3 & $\uparrow$ & 4 & 1 & 0 & 1 & 1 & Count \\ 4 & $\uparrow$ & 5 & 0 & 0 & 1 & 1 & Count \\ 5 & $\uparrow$ & 6 & 1 & 1 & 0 & 1 & Count \\ 6 & $\uparrow$ & 7 & 0 & 1 & 0 & 1 & Count \\ 7 & $\uparrow$ & 8 & 1 & 0 & 0 & 1 & Count \\ 8 & $\uparrow$ & 9 & 0 & 0 & 0 & 1 & Count \\ 9 & $\uparrow$ & 10 & 1 & 1 & 1 & 0 & Count \\ 10 & $\uparrow$ & 11 & 0 & 1 & 1 & 0 & Count \\ 11 & $\uparrow$ & 12 & 1 & 0 & 1 & 0 & Count \\ 12 & $\uparrow$ & 13 & 0 & 0 & 1 & 0 & Count \\ 13 & $\uparrow$ & 14 & 1 & 1 & 0 & 0 & Count \\ 14 & $\uparrow$ & 15 & 0 & 1 & 0 & 0 & Count \\ 15 & $\uparrow$ & 0 & 1 & 0 & 0 & 0 & Count \\ * & $\downarrow$ & $Q$ & * & * & * & * & Hold \\ \hline \end{tabular} \end{table} \subsection{課題 3-4} ? にはANDゲートを使用した. \begin{figure}[H] \centering \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit-cond/initial.jpg} \subcaption{Initial State} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit-cond/clk-3.jpg} \subcaption{Clocked 3 Times from Initial State} \end{minipage} \begin{minipage}[h]{0.3\textwidth} \centering \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit-cond/halt.jpg} \subcaption{Halt State} \end{minipage} \caption{4 Bits D Flipflop Counter with Halt Condition (LSB on Right)} \label{fig:a3-4-res} \end{figure} \subsubsection{観測された挙動} \begin{table}[H] \centering \caption{Observed State Transition Table of 4 Bits D Flipflop Counter with Halt Condition} \label{tab:a3-4-res-st} \begin{tabular}{cccccccl} \hline $Q$ & CK & $Q_{\text{next}}$ & $D_A$ & $D_B$ & $D_C$ & $D_D$ & Action \\ \hline 0 & $\uparrow$ & 1 & 0 & 0 & 0 & 0 & Count \\ 1 & $\uparrow$ & 2 & 1 & 1 & 1 & 1 & Count \\ 2 & $\uparrow$ & 3 & 0 & 1 & 1 & 1 & Count \\ 3 & $\uparrow$ & 4 & 1 & 0 & 1 & 1 & Count \\ 4 & $\uparrow$ & 5 & 0 & 0 & 1 & 1 & Count \\ 5 & $\uparrow$ & 6 & 1 & 1 & 0 & 1 & Count \\ 6 & $\uparrow$ & 7 & 0 & 1 & 0 & 1 & Count \\ 7 & $\uparrow$ & 7 & 1 & 0 & 0 & 1 & Halt \\ * & $\downarrow$ & $Q$ & * & * & * & * & Hold \\ \hline \end{tabular} \end{table} \subsection{応用課題 A} \cref{tab:a3-3-res-st}での状態0から状態1になる時の応答波形は\cref{fig:aa-res}となった. \begin{figure}[H] \centering \begin{minipage}[h]{0.45\textwidth} \centering \includegraphics[width=7cm]{./assets/t-2/result/signal-timing/first-second-bit.jpg} \subcaption{First and Second Bits} \end{minipage} \begin{minipage}[h]{0.45\textwidth} \centering \includegraphics[width=7cm]{./assets/t-2/result/signal-timing/third-fourth-bit.jpg} \subcaption{Third and Forth Bits} \end{minipage} \caption{Response Signals of Counter Output when State Transitions from 0 to 1} \label{fig:aa-res} \end{figure} 各出力がTC74HC74のHレベルの入力電圧に到達するまでの時間を応答時間とし, それぞれの応答時間の概算は\cref{tab:aa-res}となった. \begin{table}[H] \centering \caption{Response Time of Each Bit} \label{tab:aa-res} \begin{tabular}{cr} \hline Bit & Response Time (ns) \\ \hline 0 & 30 \\ 1 & 60 \\ 2 & 80 \\ 3 & 75 \\ \hline \end{tabular} \end{table}