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rename to assets/t-2/result/signal-timing/first-second-bit.jpg
diff --git a/assets/t-2/result/singal-timing/third-fourth-bit.jpg b/assets/t-2/result/signal-timing/third-fourth-bit.jpg
similarity index 100%
rename from assets/t-2/result/singal-timing/third-fourth-bit.jpg
rename to assets/t-2/result/signal-timing/third-fourth-bit.jpg
diff --git a/out/report_t-2.pdf b/out/report_t-2.pdf
index 89b455c..a8b6865 100644
Binary files a/out/report_t-2.pdf and b/out/report_t-2.pdf differ
diff --git a/out/report_t-2.synctex.gz b/out/report_t-2.synctex.gz
index 2421177..ca15886 100644
Binary files a/out/report_t-2.synctex.gz and b/out/report_t-2.synctex.gz differ
diff --git a/report_t-2.tex b/report_t-2.tex
index d73dcc6..861f4d6 100644
--- a/report_t-2.tex
+++ b/report_t-2.tex
@@ -15,7 +15,7 @@
 \usetikzlibrary{automata}
 
 \reportauthor{柴田健琉}
-\reporttitle{LEDの回路}
+\reporttitle{ディジタル回路}
 \reportdate{2026年}{06月}{20日}
 \turnindate{2026年}{06月}{30日}
 \schoolyear{2026}
diff --git a/sections/t-2/exp-detail.tex b/sections/t-2/exp-detail.tex
index a0b8d0d..d4be8b0 100644
--- a/sections/t-2/exp-detail.tex
+++ b/sections/t-2/exp-detail.tex
@@ -37,10 +37,11 @@ ANDゲートあるいはORゲートの動作を確認する.
 
 4つのボタンを入力とし, 出力を7セグメントLEDのドットに表示させる回路を作成する.
 
-\begin{figure}[tbh]
+\begin{figure}[H]
     \centering
-    \begin{circuitikz}
+    \begin{circuitikz}[scale=0.75]
         \ctikzset{logic ports=ieee}
+        \ctikzset{logic ports/scale=0.75}
         \node (A) at (0,2) {$A_{\text{IN}}$};
         \node (B) at (0,1) {$B_{\text{IN}}$};
         \node (C) at (0,0) {$C_{\text{IN}}$};
@@ -65,10 +66,11 @@ ANDゲートあるいはORゲートの動作を確認する.
 
 4つのボタンを入力とし, 出力を7セグメントLEDのドットに表示させる回路を作成する.
 
-\begin{figure}[tbh]
+\begin{figure}[H]
     \centering
-    \begin{circuitikz}
+    \begin{circuitikz}[scale=0.75]
         \ctikzset{logic ports=ieee}
+        \ctikzset{logic ports/scale=0.75}
         \node (A) at (0,2) {$A_{\text{IN}}$};
         \node (B) at (0,1) {$B_{\text{IN}}$};
         \node (C) at (0,0) {$C_{\text{IN}}$};
@@ -100,17 +102,50 @@ ANDゲートあるいはORゲートの動作を確認する.
 
 \subsection{課題3-1}
 
-論理ゲートを組み合わせてRSフリップフロップを作成し, 動作を確認する.
+論理ゲートを組み合わせて\cref{fig:a3-1-cd}のRSフリップフロップを作成し, 動作を確認する.
+
+\begin{figure}[H]
+    \centering
+    \begin{circuitikz}[scale=0.75]
+        \ctikzset{logic ports=ieee}
+        \ctikzset{logic ports/scale=0.75}
+        \ctikzset{diodes/scale=0.5}
+        \ctikzset{resistors/scale=0.5}
+        \ctikzset{switches/scale=0.75}
+
+        \node [or port] at (0,1.5) (or1){};
+        \node [or port] at (0,-1.5) (or2){};
+        \node [not port] at (3,1.5) (not1){};
+        \node [not port] at (3,-1.5) (not2){};
+
+        \draw (or1.out) -- (not1.in) (or2.out) -- (not2.in);
+        \draw (not1.out) -- ++(1,0) to [short, *-] ++(0,-0.5) coordinate(p1);
+        \draw (not2.out) -- ++(1,0) to [short, *-] ++(0,0.5) coordinate(p2);
+        \draw (or1.in 2) -- ++(0,-0.5) coordinate (p3);
+        \draw (or2.in 1) -- ++(0,0.5) coordinate (p4);
+        \draw (p1) -- (p4) (p2) -- (p3);
+        \draw ($(not1.out) + (1,0)$) -- ++(4,0) -- ++(0,-2) to[leDo, l={$D_D$}] ++(0,-1) to[R, l={$330 \ \Omega$}] ++(0,-1) node[ground]{};
+        \draw ($(not2.out) + (1,0)$) -- ++(1,0) -- ++(0,2) -- ++(1,0)  -- ++(0,-1) to[leDo, l={$D_C$}] ++(0,-1) to[R, l={$330 \ \Omega$}] ++(0,-1) node[ground]{};
+
+        \draw (-8,3) node[vcc]{$V_{DD}$} -- ++(0,-1.5) coordinate (v);
+        \draw (v) to [normal open switch] ++(4,0) coordinate (in1) -- ++(0.5,0) |- (or1.in 1) (in1) to [short, *-] ++(0,-2) to [leDo, l={$D_B$}] ++(0,-1) to [R, l={$330 \ \Omega$}] ++(0,-1) node[ground]{};
+        \draw (v) -- ++(0,-1) to [normal open switch] ++(1.5,0) coordinate (in2) -- ++(0.5,0) -| ($(or2.in 2) + (-0.5,0)$) -- (or2.in 2) (in2) to [short, *-] ++(0,-1) to [leDo, l={$D_A$}] ++(0,-1) to [R, l={$330 \ \Omega$}] ++(0,-1) node[ground]{};
+    \end{circuitikz}
+    \caption{Circuit Diagram of Assignment 3-1}
+    \label{fig:a3-1-cd}
+\end{figure}
 
 \subsection{課題3-2}
 
 DフリップフロップICを用いて\cref{fig:a3-2-cd}の回路を作成し, 動作を確認する.
 
-\begin{figure}[tbh]
+\begin{figure}[H]
     \centering
-    \begin{circuitikz}
+    \begin{circuitikz}[scale=0.9]
         \ctikzset{logic ports=ieee}
         \ctikzset{flipflops/scale=0.75}
+        \ctikzset{resistors/scale=0.75}
+        \ctikzset{diodes/scale=0.75}
         \node [flipflop D] at (0,0) (Df){};
         
         \draw (-2.5,2) node[vcc]{$V_{DD}$} -- ++(0,-0.5) to[normal open switch] ++(0,-1.5) coordinate(x) to[leDo, l={$D_p$}] ++(0,-2) to[R={$330 \Omega$}] ++(0,-2) node[ground]{};
@@ -126,9 +161,9 @@ DフリップフロップICを用いて\cref{fig:a3-2-cd}の回路を作成し,
 
 DフリップフロップICを2個用いて\cref{fig:a3-3-cd}の順列回路を作成し, 動作を確認する.
 
-\begin{figure}[tbh]
+\begin{figure}[H]
     \centering
-    \begin{circuitikz}[scale=0.9]
+    \begin{circuitikz}
         \ctikzset{logic ports=ieee}
         \ctikzset{flipflops/scale=0.75}
         \ctikzset{resistors/scale=0.75}
@@ -164,7 +199,7 @@ DフリップフロップICを2個用いて\cref{fig:a3-3-cd}の順列回路を
 
 \cref{fig:a3-4-cd}の順序回路を組み, 動作を確認する. ? に適切な論理ゲートを使用する.
 
-\begin{figure}[tbh]
+\begin{figure}[H]
     \centering
     \begin{circuitikz}
         \ctikzset{logic ports=ieee}
diff --git a/sections/t-2/exp-result.tex b/sections/t-2/exp-result.tex
index e313a8e..df930bb 100644
--- a/sections/t-2/exp-result.tex
+++ b/sections/t-2/exp-result.tex
@@ -2,35 +2,568 @@
 
 \subsection{課題 1-1}
 
-74HC08のANDゲートを使用した.
+\subsubsection{動作}
 
-\begin{figure}[tbh]
+\begin{figure}[H]
     \centering
     \begin{minipage}[h]{0.3\textwidth}
-        \includegraphics[]{./assets/t-2/result/and-gate/state-00.jpg}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/and-gate/state-00.jpg}
         \subcaption{$a = 0, \ b = 0$}
     \end{minipage}
     \begin{minipage}[h]{0.3\textwidth}
-        \includegraphics[]{./assets/t-2/result/and-gate/state-01.jpg}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/and-gate/state-01.jpg}
         \subcaption{$a = 1, \ b = 0$}
     \end{minipage}
     \begin{minipage}[h]{0.3\textwidth}
-        \includegraphics[]{./assets/t-2/result/and-gate/state-11.jpg}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/and-gate/state-11.jpg}
         \subcaption{$a = 1, \ b = 1$}
     \end{minipage}
-    \caption{74HC08 AND Gate ($x = a \cdot b$)}
+    \caption{74HC08 AND Gate, Input A on Second from Right ($x = a \cdot b$)}
+    \label{fig:a1-1-res}
 \end{figure}
 
+\subsubsection{観測された真理値表}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed Truth Table of $x = a \cdot b$}
+    \label{tab:a1-1-res-tt}
+    \begin{tabular}{ccc}
+        \hline
+        a & b & $x$ \\
+        \hline
+        0 & 0 & 0 \\
+        1 & 0 & 0 \\
+        0 & 1 & 0 \\
+        1 & 1 & 1 \\
+        \hline
+    \end{tabular}
+\end{table}
+
 \subsection{課題 1-2}
+
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/nand-4/state-0000.jpg}
+        \subcaption{$a = 0, \ b = 0, \ c = 0, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/nand-4/state-0011.jpg}
+        \subcaption{$a = 1, \ b = 1, \ c = 0, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/nand-4/state-1111.jpg}
+        \subcaption{$a = 1, \ b = 1, \ c = 1, \ d = 1$}
+    \end{minipage}
+\end{figure}
+
+\subsubsection{観測された真理値表}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed Truth Table of $x = \overline{a \cdot b \cdot c \cdot d}$}
+    \label{tab:a1-2-res-tt}
+    \begin{tabular}{ccccc}
+        \hline
+        a & b & c & d & x \\
+        \hline
+        0 & 0 & 0 & 0 & 1 \\
+        1 & 0 & 0 & 0 & 1 \\
+        0 & 1 & 0 & 0 & 1 \\
+        1 & 1 & 0 & 0 & 1 \\
+        0 & 0 & 1 & 0 & 1 \\
+        1 & 0 & 1 & 0 & 1 \\
+        0 & 1 & 1 & 0 & 1 \\
+        1 & 1 & 1 & 0 & 1 \\
+        0 & 0 & 0 & 1 & 1 \\
+        1 & 0 & 0 & 1 & 1 \\
+        0 & 1 & 0 & 1 & 1 \\
+        1 & 1 & 0 & 1 & 1 \\
+        0 & 0 & 1 & 1 & 1 \\
+        1 & 0 & 1 & 1 & 1 \\
+        0 & 1 & 1 & 1 & 1 \\
+        1 & 1 & 1 & 1 & 0 \\
+        \hline
+    \end{tabular}
+\end{table}
+
 \subsection{課題 1-3}
+
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/and-4/state-0000.jpg}
+        \subcaption{$a = 0, \ b = 0, \ c = 0, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/and-4/state-0010.jpg}
+        \subcaption{$a = 0, \ b = 1, \ c = 0, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/and-4/state-1111.jpg}
+        \subcaption{$a = 1, \ b = 1, \ c = 1, \ d = 1$}
+    \end{minipage}
+    \caption{
+        \parbox[t]{7.5cm}{4 Inputs AND Gate with Three 2 Inputs AND Gates, \\ Input A on Most Left ($x = (a \cdot b) \cdot (c \cdot d)$)}
+    }
+    \label{fig:a1-3-res}
+\end{figure}
+
+\subsubsection{観測された真理値表}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed Truth Table of $x = (a \cdot b) \cdot (c \cdot d)$}
+    \label{tab:a1-3-res-tt}
+    \begin{tabular}{ccccc}
+        \hline
+        a & b & c & d & x \\
+        \hline
+        0 & 0 & 0 & 0 & 0 \\
+        1 & 0 & 0 & 0 & 0 \\
+        0 & 1 & 0 & 0 & 0 \\
+        1 & 1 & 0 & 0 & 0 \\
+        0 & 0 & 1 & 0 & 0 \\
+        1 & 0 & 1 & 0 & 0 \\
+        0 & 1 & 1 & 0 & 0 \\
+        1 & 1 & 1 & 0 & 0 \\
+        0 & 0 & 0 & 1 & 0 \\
+        1 & 0 & 0 & 1 & 0 \\
+        0 & 1 & 0 & 1 & 0 \\
+        1 & 1 & 0 & 1 & 0 \\
+        0 & 0 & 1 & 1 & 0 \\
+        1 & 0 & 1 & 1 & 0 \\
+        0 & 1 & 1 & 1 & 0 \\
+        1 & 1 & 1 & 1 & 1 \\
+        \hline
+    \end{tabular}
+\end{table}
+
 \subsection{課題 1-4}
 
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/nand-from-ands/state-0000.jpg}
+        \subcaption{$a = 0, \ b = 0, \ c = 0, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/nand-from-ands/state-0101.jpg}
+        \subcaption{$a = 1, \ b = 0, \ c = 1, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/nand-from-ands/state-1111.jpg}
+        \subcaption{$a = 1, \ b = 1, \ c = 1, \ d = 1$}
+    \end{minipage}
+    \caption{
+        \parbox[t]{8cm}{4 Inputs NAND Gate with Three 2 Inputs AND Gates and \\ a NOT Gate, Input A on Most Left ($x = \overline{(a \cdot b) \cdot (c \cdot d)}$)}
+    }
+    \label{fig:a1-4-res}
+\end{figure}
+
+\subsubsection{観測された真理値表}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed Truth Table of $x = \overline{(a \cdot b) \cdot (c \cdot d)}$}
+    \label{tab:a1-2-res-tt}
+    \begin{tabular}{ccccc}
+        \hline
+        a & b & c & d & x \\
+        \hline
+        0 & 0 & 0 & 0 & 1 \\
+        1 & 0 & 0 & 0 & 1 \\
+        0 & 1 & 0 & 0 & 1 \\
+        1 & 1 & 0 & 0 & 1 \\
+        0 & 0 & 1 & 0 & 1 \\
+        1 & 0 & 1 & 0 & 1 \\
+        0 & 1 & 1 & 0 & 1 \\
+        1 & 1 & 1 & 0 & 1 \\
+        0 & 0 & 0 & 1 & 1 \\
+        1 & 0 & 0 & 1 & 1 \\
+        0 & 1 & 0 & 1 & 1 \\
+        1 & 1 & 0 & 1 & 1 \\
+        0 & 0 & 1 & 1 & 1 \\
+        1 & 0 & 1 & 1 & 1 \\
+        0 & 1 & 1 & 1 & 1 \\
+        1 & 1 & 1 & 1 & 0 \\
+        \hline
+    \end{tabular}
+\end{table}
+
 \subsection{課題 2-1}
+
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/7seg-bcd/state-0.jpg}
+        \subcaption{$a = 0, \ b = 0, \ c = 0, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/7seg-bcd/state-7.jpg}
+        \subcaption{$a = 1, \ b = 1, \ c = 1, \ d = 0$}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/7seg-bcd/invalid.jpg}
+        \subcaption{$a = 0, \ b = 1, \ c = 0, \ d = 1$}
+    \end{minipage}
+    \caption{7 Segment Driver (4 Bits BDC Input, LSB on Left)}
+    \label{fig:a2-1-res}
+\end{figure}
+
+\subsubsection{観測された真理値表}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed Truth Table of 7 Segment Driver}
+    \label{tab:a2-1-res-tt}
+    \begin{tabular}{ccccccccccc}
+        \hline
+        a & b & c & d & A & B & C & D & E & F & G \\
+        \hline
+        0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 0 \\
+        1 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 \\
+        0 & 1 & 0 & 0 & 1 & 1 & 0 & 1 & 1 & 0 & 1 \\
+        1 & 1 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 1 \\
+        0 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 1 & 1 \\
+        1 & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 \\
+        0 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 1 \\
+        1 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 0 \\
+        0 & 0 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\ 
+        1 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 1 & 1 \\
+        0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 
+        1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
+        0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
+        1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
+        0 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
+        1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
+        \hline
+    \end{tabular}
+\end{table}
+
 \subsection{課題 2-2B}
 
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-a.jpg}
+        \subcaption{$a = 0, \ b = 1, \ c = 0, \ d = 1$}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-b.jpg}
+        \subcaption{$a = 1, \ b = 1, \ c = 0, \ d = 1$}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-c.jpg}
+        \subcaption{$a = 0, \ b = 0, \ c = 1, \ d = 1$}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-d.jpg}
+        \subcaption{$a = 1, \ b = 0, \ c = 1, \ d = 1$}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-e.jpg}
+        \subcaption{$a = 0, \ b = 1, \ c = 1, \ d = 1$}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/state-f.jpg}
+        \subcaption{$a = 1, \ b = 1, \ c = 1, \ d = 1$}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/7seg-hexa/invalid.jpg}
+        \subcaption{$a = 1, \ b = 0, \ c = 0, \ d = 1$}
+    \end{minipage}
+    \hspace{0.45\textwidth}
+    \caption{7 Segment Hexadecimal Decoder 10-15 Only (4 Bits BCD Input, LSB on Left)}
+    \label{fig:a2-2b-res}
+\end{figure}
+
+\subsubsection{観測された真理値表}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed Truth Table of 7 Segment Hexadecimal Decoder (* Indicates Don't Care Term)}
+    \label{tab:a2-2b-res-tt}
+    \begin{tabular}{ccccccccccc}
+        \hline
+        a & b & c & d & A & B & C & D & E & F & G \\
+        \hline
+        * & * & * & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
+        * & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
+        0 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 1 & 1 \\
+        1 & 1 & 0 & 1 & 0 & 0 & 1 & 1 & 1 & 1 & 1 \\
+        0 & 0 & 1 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 \\
+        1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 1 \\
+        0 & 1 & 1 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 1 \\
+        1 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 \\
+        \hline
+    \end{tabular}
+\end{table}
+
 \subsection{課題 3-1}
+
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/rs-ff/initial.jpg}
+        \subcaption{Initial State}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/rs-ff/s-hold.jpg}
+        \subcaption{Set Hold}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/rs-ff/s-release.jpg}
+        \subcaption{Set Release}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=5cm]{./assets/t-2/result/rs-ff/r-hold.jpg}
+        \subcaption{Reset Hold}
+    \end{minipage}
+    \caption{
+        \parbox[t]{8cm}{RS Latch with OR Gates and NOT Gates (LEDs Represent Set, Reset, Inverted Output, Output from Left)}
+    }
+    \label{fig:a3-1-res}
+\end{figure}
+
+\subsubsection{観測された挙動}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed State Transition Table of RS Latch}
+    \label{tab:a3-1-res-st}
+    \begin{tabular}{ccccl}
+        \hline
+        $R$ & $S$ & $Q$ & $\overline{Q}$ & Action \\
+        \hline
+        0 & 0 & $Q$ & $\overline{Q}$ & Hold \\
+        0 & 1 & 1 & 0 & Set \\
+        1 & 0 & 0 & 1 & Reset \\
+        1 & 1 & X & X & Unstable Behaviour \\
+        \hline
+    \end{tabular}
+\end{table}
+
 \subsection{課題 3-2}
+
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff/initial.jpg}
+        \subcaption{Initial State}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff/clk-1.jpg}
+        \subcaption{Clocked Once from Initial State}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff/clk-2.jpg}
+        \subcaption{Clocked Twice from Initial State}
+    \end{minipage}
+    \caption{D Flipflop Toggler}
+    \label{fig:a3-2-res}
+\end{figure}
+
+\subsubsection{観測された挙動}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed State Transition Table of D Flipflop Toggler}
+    \label{tab:a3-2-res-st}
+    \begin{tabular}{cccl}
+        \hline
+        $CK$ & $Q$ & $Q_{\text{next}}$ & Action \\
+        \hline
+        $\uparrow$ & 0 & 1 & Toggle \\
+        $\uparrow$ & 1 & 0 & Toggle \\
+        $\downarrow$ & * & Q & Hold \\
+        \hline
+    \end{tabular}
+\end{table}
+
 \subsection{課題 3-3}
+
+\subsubsection{動作}
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit/initial.jpg}
+        \subcaption{Initial State}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit/clk-6.jpg}
+        \subcaption{Clocked Six Times from Initial State}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit/clk-15.jpg}
+        \subcaption{Clocked Fifteen Times from Initial State}
+    \end{minipage}
+    \caption{4 Bits D Flipflop Counter (LSB on Right)}
+    \label{fig:a3-3-res}
+\end{figure}
+
+\subsubsection{観測された挙動}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed State Transition Table of 4 Bits D Flipflop Counter}
+    \label{tab:a3-3-res-st}
+    \begin{tabular}{cccccccl}
+        \hline
+        $Q$ & CK & $Q_{\text{next}}$ & $D_A$ & $D_B$ & $D_C$ & $D_D$ & Action \\
+        \hline
+        0 & $\uparrow$ & 1 & 0 & 0 & 0 & 0 & Count \\
+        1 & $\uparrow$ & 2 & 1 & 1 & 1 & 1 & Count \\
+        2 & $\uparrow$ & 3 & 0 & 1 & 1 & 1 & Count \\
+        3 & $\uparrow$ & 4 & 1 & 0 & 1 & 1 & Count \\
+        4 & $\uparrow$ & 5 & 0 & 0 & 1 & 1 & Count \\
+        5 & $\uparrow$ & 6 & 1 & 1 & 0 & 1 & Count \\
+        6 & $\uparrow$ & 7 & 0 & 1 & 0 & 1 & Count \\
+        7 & $\uparrow$ & 8 & 1 & 0 & 0 & 1 & Count \\
+        8 & $\uparrow$ & 9 & 0 & 0 & 0 & 1 & Count \\
+        9 & $\uparrow$ & 10 & 1 & 1 & 1 & 0 & Count \\
+        10 & $\uparrow$ & 11 & 0 & 1 & 1 & 0 & Count \\
+        11 & $\uparrow$ & 12 & 1 & 0 & 1 & 0 & Count \\
+        12 & $\uparrow$ & 13 & 0 & 0 & 1 & 0 & Count \\
+        13 & $\uparrow$ & 14 & 1 & 1 & 0 & 0 & Count \\
+        14 & $\uparrow$ & 15 & 0 & 1 & 0 & 0 & Count \\
+        15 & $\uparrow$ & 0 & 1 & 0 & 0 & 0 & Count \\
+        * & $\downarrow$ & $Q$ & * & * & * & * & Hold \\
+        \hline
+    \end{tabular}
+\end{table}
+
 \subsection{課題 3-4}
 
+? にはANDゲートを使用した.
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit-cond/initial.jpg}
+        \subcaption{Initial State}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit-cond/clk-3.jpg}
+        \subcaption{Clocked 3 Times from Initial State}
+    \end{minipage}
+    \begin{minipage}[h]{0.3\textwidth}
+        \centering
+        \includegraphics[width=4cm]{./assets/t-2/result/d-ff-4-bit-cond/halt.jpg}
+        \subcaption{Halt State}
+    \end{minipage}
+    \caption{4 Bits D Flipflop Counter with Halt Condition (LSB on Right)}
+    \label{fig:a3-4-res}
+\end{figure}
+
+\subsubsection{観測された挙動}
+
+\begin{table}[H]
+    \centering
+    \caption{Observed State Transition Table of 4 Bits D Flipflop Counter with Halt Condition}
+    \label{tab:a3-4-res-st}
+    \begin{tabular}{cccccccl}
+        \hline
+        $Q$ & CK & $Q_{\text{next}}$ & $D_A$ & $D_B$ & $D_C$ & $D_D$ & Action \\
+        \hline
+        0 & $\uparrow$ & 1 & 0 & 0 & 0 & 0 & Count \\
+        1 & $\uparrow$ & 2 & 1 & 1 & 1 & 1 & Count \\
+        2 & $\uparrow$ & 3 & 0 & 1 & 1 & 1 & Count \\
+        3 & $\uparrow$ & 4 & 1 & 0 & 1 & 1 & Count \\
+        4 & $\uparrow$ & 5 & 0 & 0 & 1 & 1 & Count \\
+        5 & $\uparrow$ & 6 & 1 & 1 & 0 & 1 & Count \\
+        6 & $\uparrow$ & 7 & 0 & 1 & 0 & 1 & Count \\
+        7 & $\uparrow$ & 7 & 1 & 0 & 0 & 1 & Halt \\
+        * & $\downarrow$ & $Q$ & * & * & * & * & Hold \\
+        \hline
+    \end{tabular}
+\end{table}
+
 \subsection{応用課題 A}
+
+\cref{tab:a3-3-res-st}での状態0から状態1になる時の応答波形は\cref{fig:aa-res}となった.
+
+\begin{figure}[H]
+    \centering
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=6cm]{./assets/t-2/result/signal-timing/first-second-bit.jpg}
+        \subcaption{First and Second Bits}
+    \end{minipage}
+    \begin{minipage}[h]{0.45\textwidth}
+        \centering
+        \includegraphics[width=6cm]{./assets/t-2/result/signal-timing/third-fourth-bit.jpg}
+        \subcaption{Third and Forth Bits}
+    \end{minipage}
+    \caption{Response Signals of Counter Output when State Transitions from 0 to 1}
+    \label{fig:aa-res}
+\end{figure}
+
+各出力がTC74HC74のHレベルの入力電圧に達っするまでの時間を応答時間とし,
+それぞれの応答時間の概算は\cref{tab:aa-res}となった.
+
+\begin{table}[H]
+    \centering
+    \caption{Response Time of Each Bit}
+    \label{tab:aa-res}
+    \begin{tabular}{cr}
+        \hline
+        Bit & Response Time (ns) \\
+        \hline
+        0 & 30 \\
+        1 & 60 \\
+        2 & 80 \\
+        3 & 75 \\
+        \hline
+    \end{tabular}
+\end{table}
diff --git a/sections/t-2/reflection.tex b/sections/t-2/reflection.tex
index e69de29..b2c69b5 100644
--- a/sections/t-2/reflection.tex
+++ b/sections/t-2/reflection.tex
@@ -0,0 +1,6 @@
+\section{考察}
+
+\subsection{課題1-1}
+
+この実験ではTC74HC08のANDゲートを使用した.
+
diff --git a/sections/t-2/theory.tex b/sections/t-2/theory.tex
index 2828726..09b3bd9 100644
--- a/sections/t-2/theory.tex
+++ b/sections/t-2/theory.tex
@@ -42,9 +42,11 @@
         \subcaption{Logical And ($x = a \cdot b$)}
         \begin{tabular}{ccc}
             \hline
-            a \textbackslash \ b & 0 & 1 \\ \hline
+            a & b & x \\ \hline
             0 & 0 & 0 \\
-            1 & 0 & 1 \\
+            1 & 0 & 0 \\
+            0 & 1 & 0 \\
+            1 & 1 & 1 \\
             \hline
         \end{tabular}
     \end{minipage}
@@ -53,8 +55,10 @@
         \subcaption{Logical Or ($x = a + b$)}
         \begin{tabular}{ccc}
             \hline
-            a \textbackslash \ b & 0 & 1 \\ \hline
-            0 & 0 & 1 \\
+            a & b & x \\ \hline
+            0 & 0 & 0 \\
+            1 & 0 & 1 \\
+            0 & 1 & 1 \\
             1 & 1 & 1 \\
             \hline
         \end{tabular}