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\section{考察}
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\subsection{課題1-1}
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\subsection{課題 1-1}
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この実験ではTC74HC08のANDゲートを使用した.
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ANDゲートは等価回路は\cref{fig:and-gate-equi}のようにスイッチが2つ直列に接続された回路で, 両方のスイッチが閉じた時のみ, Hレベルを出力する.
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\begin{figure}[H]
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\centering
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\begin{circuitikz}
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\ctikzset{switches/scale=1}
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\ctikzset{resistors/scale=1}
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\ctikzset{diodes/scale=1}
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\draw (0,0) node[vcc]{$V_{DD}$} to [normal open switch, l={$A$}] ++(2,0) to [normal open switch, l={$B$}] ++(2,0) coordinate (out) to [R] ++(2,0) node[ground]{};
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\draw (out) to [short, *-o] ++(0,0.5) node[above]{Output};
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\end{circuitikz}
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\caption{AND Gate Equivalent Circuit}
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\label{fig:and-gate-equi}
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\end{figure}
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このことから, \cref{tab:a1-1-res-tt}で示した結果は両方の入力がHレベルの時だけ出力がHレベルとなっているため, 理論と一致することが分かる.
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\subsection{課題 1-2}
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\Cref{tab:a1-2-res-tt}より, 全ての入力がHレベルの時のみ出力がLレベルとなっている.
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NANDゲートはANDゲートの否定なので, 結果は理屈に沿っている.
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\subsection{課題 1-3}
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\Cref{fig:a1-3-cd}より, 各ゲートの出力は\cref{equ:output-of-each-gate-a1-3}となる.
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\begin{equation}
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\label{equ:output-of-each-gate-a1-3}
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\begin{split}
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O_1 &= A_{\text{IN}} \cdot B_{\text{IN}} \\
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O_2 &= C_{\text{IN}} \cdot D_{\text{IN}} \\
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D_p &= O_1 \cdot O_2 = (A_{\text{IN}} \cdot B_{\text{IN}}) \cdot (C_{\text{IN}} \cdot D_{\text{IN}})
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\end{split}
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\end{equation}
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\Cref{equ:output-of-each-gate-a1-3}より, 真理値表は\cref{tab:theoretical-a1-3}となる.
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\begin{table}[H]
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\centering
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\caption{Theoretical Truth Table of $D_p = (A_{\text{IN}} \cdot B_{\text{IN}}) \cdot (C_{\text{IN}} \cdot D_{\text{IN}})$}
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\label{tab:theoretical-a1-3}
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\begin{tabular}{ccccc}
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\hline
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$A_{\text{IN}}$ & $B_{\text{IN}}$ & $C_{\text{IN}}$ & $D_{\text{IN}}$ & $D_p$ \\
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\hline
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0 & 0 & 0 & 0 & 0 \\
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1 & 0 & 0 & 0 & 0 \\
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0 & 1 & 0 & 0 & 0 \\
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1 & 1 & 0 & 0 & 0 \\
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0 & 0 & 1 & 0 & 0 \\
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1 & 0 & 1 & 0 & 0 \\
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0 & 1 & 1 & 0 & 0 \\
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1 & 1 & 1 & 0 & 0 \\
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0 & 0 & 0 & 1 & 0 \\
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1 & 0 & 0 & 1 & 0 \\
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0 & 1 & 0 & 1 & 0 \\
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1 & 1 & 0 & 1 & 0 \\
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0 & 0 & 1 & 1 & 0 \\
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1 & 0 & 1 & 1 & 0 \\
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0 & 1 & 1 & 1 & 0 \\
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1 & 1 & 1 & 1 & 1 \\
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\hline
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\end{tabular}
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\end{table}
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\Cref{tab:theoretical-a1-3}より, 出力$D_p$が1となるのは全入力が1の時だけであり, この条件を論理式にすると\cref{equ:a1-3-final}となり, \cref{equ:output-of-each-gate-a1-3}で示した$D_p$と等価な式になる.
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\begin{equation}
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\label{equ:a1-3-final}
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d_p = A_{\text{IN}} \cdot B_{\text{IN}} \cdot C_{\text{IN}} \cdot D_{\text{IN}}
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\end{equation}
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\subsection{課題 1-4}
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\Cref{fig:a1-4-cd}の出力は\cref{equ:a1-4-out}で示され, ド・モルガンの定理で変形していくと\cref{equ:a1-4-de-morganed}となる.
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\begin{equation}
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\label{equ:a1-4-out}
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D_p = \overline{(A_{\text{IN}} \cdot B_{\text{IN}}) \cdot (C_{\text{IN}} \cdot D_{\text{IN}})}
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\end{equation}
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\begin{equation}
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\label{equ:a1-4-de-morganed}
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\begin{split}
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D_p &= \overline{(A_{\text{IN}} \cdot B_{\text{IN}}) \cdot (C_{\text{IN}} \cdot D_{\text{IN}})} = \overline{A_{\text{IN}} \cdot B_{\text{IN}}} + \overline{C_{\text{IN}} \cdot D_{\text{IN}}} \\
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&= \overline{A_{\text{IN}}} + \overline{B_{\text{IN}}} + \overline{C_{\text{IN}}} + \overline{D_{\text{IN}}} = \overline{A_{\text{IN}} \cdot B_{\text{IN}} \cdot C_{\text{IN}} \cdot D_{\text{IN}}}
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\end{split}
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\end{equation}
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\Cref{equ:a1-4-de-morganed}より,
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\Cref{tab:a1-4-res-tt}の真理値表は\cref{tab:a1-2-res-tt}のものと一致している.
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論理式の等価は真理値表の一致を意味するので, \cref{equ:a1-4-de-morganed}で示した論理式の真理値表も全て一致する.
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\subsection{課題 2-1}
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デコーダ回路とはある意味を持つコードを別の対応するコードへの写像を取る回路のことである.
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今回の場合は4ビットの二進数から7セグメントLEDの点灯パターンへの写像を論理回路で実装している.
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7セグメントLEDデコーダのTC4511はそれぞれの出力が論理式の出力となってる.
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\subsection{課題 2-2B}
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この回路を制作するにあたって, まずは\cref{tab:a2-2b-tt-design}の真理値表を考える.
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\begin{table}[H]
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\centering
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\caption{Truth Table for Designing 7 Segment Hexadecimal Decoder}
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\label{tab:a2-2b-tt-design}
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\begin{tabular}{ccccccccccc}
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\hline
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a & b & c & d & A & B & C & D & E & F & G \\
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\hline
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0 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 1 & 1 \\
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1 & 1 & 0 & 1 & 0 & 0 & 1 & 1 & 1 & 1 & 1 \\
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0 & 0 & 1 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 \\
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1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 1 \\
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0 & 1 & 1 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 1 \\
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1 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 \\
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\hline
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\end{tabular}
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\end{table}
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ここで, dの値が全てHレベルであるので, 一旦省略する.
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この真理値表にもとずいたそれぞれのセグメントの論理式は\cref{equ:a2-2b-equ-design}となる.
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\begin{equation}
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\label{equ:a2-2b-equ-design}
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\begin{split}
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A &= \overline{(a \cdot b \cdot \bar{c}) + (a \cdot \bar{b} \cdot c)} \\
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B &= (\bar{a} \cdot b \cdot \bar{c}) + (a \cdot \bar{b} \cdot c) \\
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C &= B + (a \cdot b \cdot \bar{c}) \\
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D &= \overline{(\bar{a} \cdot b \cdot \bar{c}) + (a \cdot b \cdot c)} \\
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E &= 1 \\
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F &= \overline{a \cdot \bar{b} \cdot c} \\
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G &= \overline{\bar{a} \cdot \bar{b} \cdot c}
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\end{split}
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\end{equation}
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これら論理式にカルノー図を適応したが, もとが十分簡略化されているためか, あまり有用ではなかった.
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かわりに, 複数式の共通する項を1つのユニットとして共有して使用することにした.
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共通項は\cref{equ:a2-2b-common}とした.
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\begin{equation}
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\label{equ:a2-2b-common}
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\begin{split}
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X &= (a \cdot b \cdot \bar{c}) \\
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Y &= (a \cdot \bar{b} \cdot c) \\
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Z &= (\bar{a} \cdot b \cdot \bar{c})
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\end{split}
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\end{equation}
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また, 禁止条件が入力された際の真理値値表は\cref{tab:a2-2b-not-allowed}となった.
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\begin{table}[H]
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\centering
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\caption{Truth Table for Disallowed Conditions}
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\label{tab:a2-2b-not-allowed}
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\begin{tabular}{ccccc}
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\hline
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a & b & c & d & $\overline{\text{EN}}$ \\
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\hline
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* & * & * & 0 & 1 \\
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* & 0 & 0 & 1 & 1 \\
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\hline
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\end{tabular}
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\end{table}
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上記の真理値表から論理式を作成すると\cref{equ:a2-2b-not-allowed-equ}となった.
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\begin{equation}
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\label{equ:a2-2b-not-allowed-equ}
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\text{EN} = d \cdot (b + c)
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\end{equation}
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これら論理式から回路を制作すると\cref{fig:a2-2b-cd}となった.
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\begin{figure}[tbh]
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\centering
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\begin{circuitikz}[scale=0.7]
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\ctikzset{logic ports=ieee}
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\ctikzset{logic ports/scale=0.7}
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\ctikzset{resistors/scale=0.7}
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\node [and port, number inputs=3] at (-5,4) (X) {};
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\node [and port, number inputs=3] at (-5,2) (Y) {};
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\node [and port, number inputs=3] at (-5,0) (Z) {};
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\node [nor port] at (0,4) (A) {};
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\node [or port] at (0,2) (B) {};
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\node [or port] at (0,0) (C) {};
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\node [and port, number inputs=3] at (5,4) (m) {};
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\node [nor port, anchor=in 2] at ($(m.out) + (1,0)$) (D) {};
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\node [not port] at (5,2) (F) {};
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\node [nand port, number inputs=3] at (5,0) (G) {};
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\node [notcirc,left] at (X.bin 3) {};
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\node [notcirc,left] at (Y.bin 2) {};
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\node [notcirc,left] at (Z.bin 1) {};
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\node [notcirc,left] at (Z.bin 3) {};
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\node [notcirc,left] at (G.bin 1) {};
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\node [notcirc,left] at (G.bin 2) {};
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\draw (X.in 1) ++(-0.5,0) node[left]{a} to [short, o-] (X.in 1);
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\draw (X.in 2) ++(-0.5,0) node[left]{b} to [short, o-] (X.in 2);
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\draw (X.in 3) ++(-0.5,0) node[left]{c} to [short, o-] (X.in 3);
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\draw (X.out) to [short, -o] ++(0.5,0) node[right]{X};
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\draw (Y.in 1) ++(-0.5,0) node[left]{a} to [short, o-] (Y.in 1);
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\draw (Y.in 2) ++(-0.5,0) node[left]{b} to [short, o-] (Y.in 2);
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\draw (Y.in 3) ++(-0.5,0) node[left]{c} to [short, o-] (Y.in 3);
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\draw (Y.out) to [short, -o] ++(0.5,0) node[right]{Y};
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\draw (Z.in 1) ++(-0.5,0) node[left]{a} to [short, o-] (Z.in 1);
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\draw (Z.in 2) ++(-0.5,0) node[left]{b} to [short, o-] (Z.in 2);
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\draw (Z.in 3) ++(-0.5,0) node[left]{c} to [short, o-] (Z.in 3);
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\draw (Z.out) to [short, -o] ++(0.5,0) node[right]{Z};
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\draw (A.in 1) ++(-0.5,0) node[left]{X} to [short, o-] ++(0.5,0);
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\draw (A.in 2) ++(-0.5,0) node[left]{Y} to [short, o-] ++(0.5,0);
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\draw (A.out) to [short, -o] ++(0.5,0) node[right]{A};
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\draw (B.in 1) ++(-0.5,0) node[left]{Y} to [short, o-] ++(0.5,0);
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\draw (B.in 2) ++(-0.5,0) node[left]{Z} to [short, o-] ++(0.5,0);
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\draw (B.out) to [short, -o] ++(0.5,0) node[right]{B};
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\draw (C.in 1) ++(-0.5,0) node[left]{B} to [short, o-] ++(0.5,0);
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\draw (C.in 2) ++(-0.5,0) node[left]{X} to [short, o-] ++(0.5,0);
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\draw (C.out) to [short, -o] ++(0.5,0) node[right]{C};
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\draw (m.in 1) ++(-0.5,0) node[left]{a} to [short, o-] ++(0.5,0);
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\draw (m.in 2) ++(-0.5,0) node[left]{b} to [short, o-] ++(0.5,0);
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\draw (m.in 3) ++(-0.5,0) node[left]{c} to [short, o-] ++(0.5,0);
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\draw (m.out) -- (D.in 2);
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\draw (D.in 1) ++(-0.5,0) node[left]{Z} to [short, o-] ++(0.5,0);
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\draw (D.out) to [short, -o] ++(0.5,0) node[right]{D};
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\draw (F.in) ++(-0.5,0) node[left]{Y} to [short, o-] ++(0.5,0);
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\draw (F.out) to [short, -o] ++(0.5,0) node[right]{F};
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\draw (G.in 1) ++(-0.5,0) node[left]{a} to [short, o-] (G.in 1);
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\draw (G.in 2) ++(-0.5,0) node[left]{b} to [short, o-] (G.in 2);
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\draw (G.in 3) ++(-0.5,0) node[left]{c} to [short, o-] (G.in 3);
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\draw (G.out) to [short, -o] ++(0.5,0) node[right]{G};
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\draw (G.out) ++(0,-2) node[above]{$\text{7seg}_\text{GND}$} to [short, o-] ++(0,-1) node[nigfete,anchor=D](Q){} (Q.S) -- ++(0,-1.3) node[ground]{} (Q.G) to [short, -*] ++(-1,0) coordinate (Qin) to [R, l={$330 \ \Omega$}] ++(0,-2) node[ground]{};
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\draw (Qin) -- ++(-1,0) node[and port, anchor=out](ENAnd){};
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\draw (ENAnd.in 1) to [short, -o] ++(-0.5,0) node[left]{d};
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\draw (ENAnd.in 2) -- ++(-1,0) node[or port, anchor=out](ENOr){};
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\draw (ENOr.in 1) to [short, -o] ++(-0.5,0) node[left]{b};
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\draw (ENOr.in 2) to [short, -o] ++(-0.5,0) node[left]{c};
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\end{circuitikz}
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\caption{Circuit Diagram of 7 Segment Hexadecimal Decoder}
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\label{fig:a2-2b-cd}
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\end{figure}
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\subsection{課題 3-3}
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\subsection{課題 3-4}
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\subsection{応用課題 A}
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